Channel Layer Surface Modifications in a-Si:II thin Film Transistors With Oxide/Nitride Dielectric Layers
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CHANNEL LAYER SURFACE MODIFICATIONS IN a-Si:I THIN FILM TRANSISTORS WITH OXIDE/NITRIDE DIELECTRIC LAYERS S.S. HE, D.J. STEPHENS, R.W. HAMAKER, AND G. LUCOVSKY Departments of Physics, Electrical and Computer Engineering, and Materials Science and Engineering, North Carolina State University, Raleigh NC 27695-8202 ABSTRACT We have fabricated normal and inverted staggered a-Si:H thin film transistors, TF~s, using silicon oxide/nitride double layer dielectrics. Significant improvements in the electrical performance of these TFTs have been obtained by integrating additional processing steps into the usual processing cycles. These include; i) a pre-deposition nitridation of the a-Si:H surface for the topgate devices, and ii) a post-deposition passivation of the a-Si:H surface (i.e., the back of the channel region) for the bottom-gate structures. Improvements in the electrical properties of the aSi:H TFTs resulting from these additional processing steps are discussed. INTRODUCTION Thin film transistors, TFTs, using a-Si:H channel regions are used as the switching devices in liquid crystal displays [.1,2]. Most TFTs devices employ silicon nitride dielectric layers, and the performance characteristics of the TFTs, are determined in part by the fixed and trapped charge in these silicon nitride dielectric layers [3-7]. The electrical characteristics of the gate dielectric are also an important factor in determining TFT reliability and process yield [3,81. The interface between SiO 2 and a-Si:H displays significant electron depletion [31, and therefore is difficult to invert at low voltages. The interface between silicon nitride, Si 3 N4 and a-Si:H does not display significant electron depletion [3]; however, nitride dielectrics generally contain high densities of fixed charge; and active trapping sites that are associated with either departures from stoiochiometry as in Si-Si bonds, and/or significant amounts of bonded-H. These bulk defects, and/or impurities promote higher leakage currents and lower breakdown fields than in Si0 2 dielectrics, as well as significant hysteresis in device operation. We have developed composite silicon oxide/silicon nitride dielectric layers, and have integrated them into TFT device structures [9]. These double layer structures combine: i) the improved interfacial properties of the Si 3 N4 /a-Si:H; with ii) the superior bulk properties of Si0 2 , and thereby improve device performance. In other publications, we have addressed the issues relative to: i) the relationship between composition and electrical properties of silicon nitride and the performance of the TFTs 19,10]; ii) the optimization of the nitride deposition conditions to achieve TFTs with high channel mobilities [9,10]. This paper addresses issues relevant to pre-deposition, and post-metallization channel surface processing, and the way insertion of these steps can promote improved device performance. FABRICATION OF a-Si:H TFTs Tungsten-gate inverted staggered a-Si:H TFTs, and aluminum top-gate staggered TFTs have been fabricated in a
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