1T Memory Cell Based on PVDF-TrFE Field Effect Transistor
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1067-B03-02
1T Memory Cell Based on PVDF-TrFE Field Effect Transistor Giovanni Antonio Salvatore1, Didier Bouvet1, Mihai Adrian Ionescu1, Sebastian Riester2, Igor Stolichnov2, Roman Gysel2, and Nava Setter2 1 STI/IEL/LEG2, EPFL, EPFL STI IEL LEG2, ELB 237 (Bâtiment ELB), Station 11, Lausanne, 1015, Switzerland 2 EPFL / STI / IMX / LC, EPFL, EPFL STI IMX LC, MXD 231 (Bâtiment MXD), Station 12, Lausanne, 1015, Switzerland ABSTRACT Interest in vinylidene fluoride (VDF) co-polymer with trifluorethylene (TrFE) P(VDFTrFE) as ferroelectric material for memory application is driven by the prospect of having low cost and low operating voltage devices integrated on silicon and, at long term, migrate on flexible substrates. Some previous studies reported FET design using copolymers [1-8] but none of these structures were fully integrated on silicon wafers into a quasi-standard MOSFET fabrication process. We present for the first time the integration of a P(VDF-TrFE) (70%-30%) layer into a standard n-MOS transistor gate stack through a conventional semiconductor technology. This allows us to achieve a one-transistor (1T) Non Volatile Memory (NVM) cell. The operation voltage required for the 100nm organic ferroelectric thickness is less than 12V and a retention time ranging from few hours to few days is reported. FABRICATION A simple fabrication process is proposed in order to integrate the polymer and in order to make it as much as possible compatible with the CMOS technology (Fig.1). The substrate is a pdoped Si (Na=1016cm-3) with crystal orientation (100). We define the active area through Shallow Trench Isolation (STI). The source and drain regions are heavily doped (Nd=1020 cm-3) by Phosphorous Oxychloride (POCl3) and a thin film (10nm) of SiO2 is thermally grown on the substrate to reduce the leakages and the screening in the ferroelectric gate. The P(VDF-TrFE) is prepared using a new recipe based on Methyl-Ethyl-Ketone, which helps to considerably reduce the film thickness and so the coercive field. The solution is spin coated and afterwards baked for 7 minutes at 137ºC. The final layer thickness of 100nm has been measured and confirmed by an Atomic Force Microscopy (AFM). A thin gold layer (100nm) is sputtered to make the contacts and, after the last lithography, it is removed by wet etching. Based on this process, we have designed, fabricated and characterized transistors of different dimensions, ranging from 50µm down to 2µm (channel length and width) limited by the lithographic resolution available in our academic clean room. Limitations of this fabrication process are the non-uniformity and the roughness of the polymer after the spinning process. The polymer has a roughness about 38nm with a peak value of 80nm and a root mean square of 7nm. This is a limitation in reducing the operating voltage that depends on the thickness of the ferroelectric layer. Future work will also focus on studying new deposition techniques that would guarantee much better uniformity and less roughness.
1 LTO
4
LTO
n+
n+
LTO
p-doped
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