Novel Field Effect Transistor Fabrication Based on Non-Graphene 2D Materials
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Novel Field Effect Transistor Fabrication Based on Non-Graphene 2D Materials Yu-Tao Li1,2, Hai-Ming Zhao1, He Tian1, Peng-Zhi Shao1, Xin Xin1, Hui-Wen Cao1, Ning-Qin Deng1, Yi Yang1, Tian-Ling Ren*1,2 1
Institute of Microelectronics & Tsinghua National Laboratory for Information Science and Technology (TNList), Tsinghua University, Beijing 10084, China 2 State Key Laboratory of Transducer Technology, Chinese Academy of Sciences Corresponding Author E-mail: [email protected] ABSTRACT In this paper, field effect transistors (FET) based on different kinds of non-graphene materials are introduced, which are MoS2, WSe2 and black phosphorus (BP). Those devices have their unique features in fabrication process compared with conventional FETs. Among them, MoS2 FET shows better electrical characteristics by applying a SiO2 protective layer; WSe2 FET is fabricated based on a new low pressure chemical vapor deposition (LPCVD) method; BP FET acquires high on/off ratio and high hole mobility by using a simple dry transfer method. Those novel non-graphene materials inspire new design and fabrication process of basic logic device. INTRODUCTION Field effect transistor (FET) as the basic logic device plays an important role in information age. Novel two-dimensional (2D) materials show great promise for the next generation low-dimensional FET. However, the FET based on a well-known 2D material, graphene, shows bad on-off radio due to its zero bandgap property. Therefore, beyond graphene, new kinds of non-graphene materials with reasonable bandgap, such as MoS2, WSe2 and black phosphorus (BP), have attracted wide research attention. Unique FET fabrication process was designed for these non-graphene 2D materials to obtain FET with higher mobility and on-off radio. Here, three works about novel field effect transistor fabrication based on non-graphene 2D materials are presented and discussed. MoS2 FETs with a SiO2 protective layer A. Introduction Top-gate MoS2 FETs with SiO2 protective layer were fabricated to avoid the monolayer MoS2 from the influence of charged impurities and interface states by designing unique optical lithography process. As a result, the contact property between the MoS2 and the electrodes were improved and both the carrier mobility and the source-drain current were enhanced. Comparing with MoS2 FETs without a SiO2 protective layer, the SiO2 protective layer was found to enhance the transfer and output characteristics of MoS2 FETs. This work applies a practical method to enhance the MoS2 FETs performance in the low-dimensional FET fabrication process. B. Monolayer MoS2 characterization and device fabrication
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The details of monolayer MoS2 growth on SiO2/Si substrate by CVD method were referred in Ref.1. [1] The AFM image in Figure 1 (a) shows the uniformity of the MoS2 mater
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