3D Modelling Of The Novel Nanoscale Screen-Grid FET
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0913-D05-08
3D Modelling of the Novel Nanoscale Screen-Grid FET Pei W. Ding1, Kristel Fobelets1, and Jesus E. Velazquez-Perez2 1 Department of Electrical Engineering, Imperial College, London, United Kingdom 2 Departamento de Fisica Aplicada, Universidad de Salamanca, Salamanca, Spain ABSTRACT A novel field effect transistor (FET) that uses 3-dimensional (3-D) embedded gate fingers – the Screen-Grid Field Effect Transistor (SGFET) – is proposed. The gating action of the SGFET is based on the design of multiple gating cylinders into the channel region, perpendicular to the current flow. Such configuration allows a full 3-D gate control of the current which improves the device characteristics by increasing the gate to channel coupling. Initial investigations of the SGFET using 3-D TCAD TaurusTM simulation software are presented in this paper. The results indicate that the proposed SGFET offers the possibility of downscaling without degrading the output characteristics. A comparison between the SGFET and both bulk and SOI MOSFETs shows the superior characteristics of the SGFET for low power operation. INTRODUCTION Progress in semiconductor industry is determined by increased operation speed and packing density, and decreased power consumption which are obtained by means of a reduction of the geometrical parameters. Downscaling of the device dimensions goes hand-in-hand with increased short channel effects [1], such as high off-current and drain induced barrier lowering (DIBL). These can be combated, to a certain extend, via ingenious but expensive fabrication techniques, or via the introduction of novel device geometries. Both innovative device structures (e.g. finFET) and new materials (e.g. strained-Si) have been proposed for such purposes. In this work we propose a novel device geometry based on the principle of embedded gate fingers – the SGFET. The DC operation of the SGFET is investigated via TCAD using the 3-D TaurusTM simulation software [2]. The influence of the geometrical position of the gating cylinders and their dimensions on the electrical performance of the device is investigated, and compared to bulk MOSFETs and SOI MOSFETs with the same source to drain distance. DEVICE STRUCTURE AND OPERATION The proposed SGFET is based on the design of the gating cylinders perpendicular into the channel region. A particularly promising gating configuration is shown in Figure 1, but other configurations and gate finger geometries are possible. The structure is quite similar in principle to the permeable base transistor (PBT), but with reduced processing complexity, compatible with current CMOS technology [3]. Unlike the PBT, the SGFET is a unipolar device in which the type of the majority carriers is determined by the doping of the ohmic contacts and the channel region. The SGFET has to be fabricated on silicon on insulator (SOI) or strained-silicon on insulator (SSOI) [4]. Cylindrical gate fingers are embedded and defined into the SOI body perpendicular to the current flow, allowing a full 3-D gating control of the c
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