Exploring novel characteristics of strain compensated SiGeC nanoscale MOSFET
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ORIGINAL PAPER
Exploring novel characteristics of strain compensated SiGeC nanoscale MOSFET S Basu*, S K Sarkar and S K Sarkar Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700 032, India Received: 19 September 2012 / Accepted: 22 November 2012 / Published online: 7 December 2012
Abstract: In the present work a precise but simple empirical model for single gate nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFET is proposed. The threshold voltage is calculated by solving the two-dimensional (2D) Poisson equation under befitting boundary conditions incorporating short-channel effects, the effect of strain, strained-silicon thin film thickness, and gate work function. The proposed empirical model provides results comparable with those obtained from 2D device simulation thereby establishing the extent of accuracy of our present model. The empirical model so developed correctly exhibits that the threshold voltage is reduced with the increase of strain in the silicon thin film. We have investigated, herewith our proposed model, the influences of various device parameters like: strain (with minute amount of carbon and significant amount of Ge), strained-silicon thin-film thickness and gate work function on the threshold voltage. The extent of equivalent Ge content enhances the performance of the proposed MOSFET in terms of better speed because of the carrier mobility enhancement due to addition of carbon atoms. Keywords:
Strained-Si; Short channel effects; Threshold voltage
PACS Nos.: 73.40.Ty; 85.30.Tv; 85.35.–p
1. Introduction Since the carrier transit time imposes intrinsic limitations on the speed of metal oxide semiconductor field effect transistor (MOSFET), the most obvious approach to improve the device speed is to reduce the gate length [1]. But, the two-dimensional (2D) effects due to the gate length scaling affect the threshold voltage and sub-threshold slope and increase the off-state current [2]. When the gate length is aggressively scaled, the gate begins to lose control over the channel and the parasitic conduction layers results in saturation, possibly in a reduction of transconductance and in an increase of drain conductance [3]. The major problems of scaling down the conventional MOSFETs include (i) quantum mechanical tunneling through the thin gate oxide, from source to drain and from drain to body; (ii) threshold voltage control induced by random doping effects; (iii) short channel effects and mobility degradation; and (iv) process control of thin layer uniformity and accurate lithography and implantation [4, 5].
*Corresponding author, E-mail: [email protected]
Several schemes for performance boosters have been proposed in the literature and the International Technology Roadmap for semiconductors suggest that one or more technology boosters may be required for devices beyond the 45 nm technology node in order to sustain the increase of intrinsic device speed. Through relevant strain engineering such as, embedded-SiGe unde
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