CMOS-Compatible Through Silicon Vias for 3D Process Integration
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0970-Y01-01
CMOS-Compatible Through Silicon Vias for 3D Process Integration Cornelia K. Tsang1, Paul S. Andry1, Edmund J. Sprogis2, Chirag S. Patel1, Bucknell C. Webb1, Dennis G. Manzer1, and John U. Knickerbocker1 1 IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY, 10598 2 IBM Systems and Technology Group, 1000 River Street, Essex Junction, VT, 05452 ABSTRACT As the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and highdensity solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical throughvias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150 µm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated. INTRODUCTION In recent years, as the limits of CMOS scaling have been approached, many have recognized the need for alternative paths to enable the continued improvement in system-level performance. In particular, it has been noted that there exists a technology gap between the 2005 ITRS trends for off-chip interconnection and first-level packaging available [1-2]. Many two- and threedimensional sub-system solutions to meet this gap have been investigated [3-6]. At the highest levels of interconnect density, numerous CMOS 3D integrated circuit options have been suggested including sequential build-up of device levels [7] and integration of devices through bonding techniques and vertical interconnection, see Figure 1a [8]. In contrast to these chip and/or wafer level approaches, silicon carrier system-on-package is a packaging solution that enables heterogen
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