CMOS Compatible Synthesis of Carbon Nanotubes
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1081-P01-09
CMOS Compatible Synthesis of Carbon Nanotubes Takashi Uchino1, Konstantinos N. Bourdakos2, Gregory N. Ayre2, Cornelis H. de Groot1, Peter Ashburn1, and David C. Smith2 1 Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, United Kingdom 2 Physics and Astronomy, University of Southampton, Southampton, SO17 1BJ, United Kingdom ABSTRACT A technique to synthesize high-quality single walled carbon nanotubes (SWNTs) using chemical vapour deposition (CVD) on Ge Stranski-Krastanow dots has been developed. From transmission electron microscopy and Raman measurements, the grown carbon nanotubes (CNTs) are identified as SWNTs with diameters ranging from 1.6 to 2.1 nm. Extensive scanning electron microscopy and atomic force characterisation of the effect of each stage in the growth process is presented. Our hypothesis is that pre-treatment stages lead to the formation of Ge nanoparticles, which act as seeds for CNT growth. This technique demonstrates the ability to synthesize high-quality SWNTs without the need for a metal catalyst, using processes and equipment standard to a silicon foundry. INTRODUCTION The excellent electrical [1, 2], optical [3], and thermal [4] properties of carbon nanotubes make them promising materials for use in electronics. To date, a number of interesting electronic devices have been manufactured using SWNTs. These include non-volatile random access memories [5], field emission displays [6], via interconnects [7] and field effect transistors [2]. In order for these and future CNT based devices to be integrated with silicon electronics, a method for CVD growth of CNTs compatible with silicon very-large-scale-integration (VLSI) technology is essential. In particular, there is a need to avoid the standard metal catalysts used for CNT growth (typically Fe, Ni or Co), as these can create deep level defects in the Si band gap and result in trap states [8]. Other drawbacks include the high propensity for Si-metal interdiffusion, leading to the formation of silicides. In practical terms, this leads to increased leakage current, breakdown at lower voltages and a shorter device lifetime. The need for a process which would allow the integration of CNTs into any stage of the CMOS process flow has stimulated a number of recent investigations into metal-catalyst-free CNT growth methods [9-11]. The first of these is based on annealing SiC films or nanoparticles [9, 10]. However the main drawback of this approach is the high-temperature requirement (approximately 1650 °C) which makes integration problematic. Another technique is based upon hydrogenated carbon nanoparticles [11], which relies on the structural reorganization of C to produce CNT bundles. Although SWNTs have been produced using this technique, Raman scattering suggests these are structurally defective. We have previously published a method for growing CNTs from carbon ion implanted SiGe substrates [12]. This method allowed the production of SWNTs at a temperature below 1000 °C, in a standard CVD furnace. This
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