Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS
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1070-E04-04
Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub45nm CMOS Pankaj Kalra1,2, Prashant Majhi1, Hsing-Huang Tseng1, Raj Jammy1, and Tsu-Jae King Liu2 1 SEMATECH, Austin, TX, 78741 2 EECS, University of California, Berkeley, Berkeley, CA, 94720 ABSTRACT The use of millisecond annealing to meet ultra-shallow junction requirements for sub45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature Tint = 700oC (vs. 800oC). Significantly lower Rs is achieved with peak temperature Tpeak = 1300oC (vs. 1250oC). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency. INTRODUCTION One of the major challenges for MOSFET scaling in the sub-45nm regime is the formation of ultra-shallow junctions (USJs). The International Technology Roadmap for Semiconductors (ITRS) indicates that future generations of CMOS technology should have source/drain-extension junctions that are ~12-15nm deep, with sheet resistance Rs~1000 Ω/ , in order to keep pace with historical improvements in high-performance logic devices [1]. The USJ requirement stems from the need to suppress short channel effects (SCE), and dictates a very limited thermal annealing budget to limit dopant diffusion; the low sheet resistance requirement is necessary to ensure low parasitic resistance, and dictates a high annealing temperature to maximize dopant activation. These requirements are especially difficult to meet for p+/n junctions, due to boron transient enhanced diffusion (TED). Flash annealing is a potentially attractive alternative to conventional spike annealing for source/drain dopant activation, because it provides for shorter annealing time (~ms) and higher peak temperature (~1300oC). EXPERIMENTAL DETAILS Blanket USJ formation studies were performed using Si (100) wafer substrates. 2-nmthick thermal oxide was grown before ion implantation, followed by either a shallow boron implant or a shallow arsenic implant. A pre-amorphization Ge implant (20keV, 1015 cm-2) was done prior to boron implantation to eliminate ion channeling. Nitrogen and fluorine were coimplanted with boron. These co-implanted species interact with excess Si interstitials generated during implantation and reduce the impact of boron TED. A spike anneal (1070oC) or flash anneal was used to activate the implanted dopants. Figure 1 highlights the features of the flash annealing process used in this work [2]. In a flash annealing process, the wafer is first heated up to an intermediate temperature (Tint), and then a millisecond flash is applied to heat the device side of the wafer to the peak temperature (Tpeak). Various combinations of flash anneal parameters (Tint, Tpeak, and n, where n is the number of flash anneals) were included in the study
to elucidate interdependencie
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