A Low Power Approach for Designing 12-Bit Current Steering DAC
A low power 12-bit current steering DAC is designed using SCL 180-nm-technology. Various methodologies are considered to reduce the power consumption in current steering DAC. The current mode logic (CML)-based latch is incorporated to design latch cum-lev
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Abstract A low power 12-bit current steering DAC is designed using SCL 180-nmtechnology. Various methodologies are considered to reduce the power consumption in current steering DAC. The current mode logic (CML)-based latch is incorporated to design latch cum-level shifters to reduce digital power consumption. A dummy switch compensation technique is also used at the output of switch to counter the effect of charge feedthrough from switch to the output of DAC. In addition, it also reduces the minimum allowable voltage headroom, thus reducing power consumption of analog block. The power consumption obtained is 12 mW for 12-bit design operating at 200 MHz frequency. Keywords CML · LSB · INL · SFDR · Voltage headroom · Charge feedthrough
1 Introduction The extensive use of battery-operated IOTs demands the use of low power DACs for transmitters; thus, DACs are one of the key blocks for portable IOTs. Lots of architectural and technology alternative available but CMOS technology DACs have the advantage of having high-speed and low power consumption [1–4]. CMOS current steering DACs may be classified based on architectural level as: (i) unary-weighted architecture (ii) binary-weighted architecture. Unary-weighted architecture consists of unit current element arranged in thermometer encoded
A. Kumar (B) · S. K. Gupta · V. Bhadauria Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh 211004, India e-mail: [email protected] S. K. Gupta e-mail: [email protected] V. Bhadauria e-mail: [email protected] © Springer Nature Singapore Pte Ltd. 2021 D. Harvey et al. (eds.), Advances in VLSI, Communication, and Signal Processing, Lecture Notes in Electrical Engineering 683, https://doi.org/10.1007/978-981-15-6840-4_49
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ways. However, the requirement of encoder–decoder increases area [5–10]. Binaryweighted architecture consists of weighted current cell arranged in binary-weighted form, due to which its architecture is simple and occupies less area. This architecture is preferred for low power solutions [4, 11–13]. Segmented architecture is hybrid between binary-weighted and unary architecture which also requires encoder– decoder and delay element; hence, it is not preferred over binary-weighted for low power DACs. The mismatch between weighted current sources limits the resolution of binary-weighted architecture up to 10 bits [14]. However, partial segmented architecture uses the advantage of both binary-weighted and segmented architecture and thus used for higher-resolution DACs [15–17]. In this, LSB current cell is connected in serial and parallel to form weighted array without the use of encoder and decoders. There is very limited work done on the low power aspect of current steering DAC. Douglas A. Mercer [18] shows power consumption of different blocks used in current steering DAC with respect to clock frequency; however, the author used separate blocks for latch and level shifter which increases area as
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