A Petri-net-based communication-aware modeling for performance evaluation of NOC application mapping
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A Petri‑net‑based communication‑aware modeling for performance evaluation of NOC application mapping Mostafa Raeisi‑Varzaneh1 · Hossein Sabaghian‑Bidgoli1
© Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Advances in digital system manufacturing and increasing demand for high-speed applications have urged designers on using multiprocessor systems. Network on chip (NOC) is an important architecture used for implementing multiprocessor systems. The main challenge in designing a NOC is application mapping in which an efficient task-core assignment is investigated. Different types of algorithms with different objectives have been proposed by researchers. Due to the bandwidth constraint, application runtime is the most important objective in different methods. However, most of the previous works have employed a simple and inaccurate metric to evaluate the application runtime. In this work, a Petri-net-based modeling approach is presented to provide accurate estimation of the application runtime. Considering the parallelism in concurrent tasks and communications, as well as exclusion in computations and communications with common resources, is the main advantage of the presented model. The experimental results show considerable improvement in the accuracy in the proposed method compared to the previous works. Keywords Network-on-chip · System-level modeling · Application mapping · Performance evaluation · Petri-net · Communication resource sharing
1 Introduction Increasing demand for modern complex systems, in addition to the limitations of traditional design methods in meeting time to market [1], have convinced designers to utilize higher level of abstractions, namely electronic system level (ESL) [2]. ESL is the utilization of appropriate abstractions in order to increase comprehensibility of a * Hossein Sabaghian‑Bidgoli [email protected] Mostafa Raeisi‑Varzaneh [email protected] 1
Department of Computer Engineering, Faculty of Electrical and Computer Engineering, University of Kashan, Kashan, Iran
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system, and to enhance the probability of a successful implementation in a cost-effective manner, as well as meeting some necessary constraints [3]. System-level design necessitates the application of appropriate tools and languages for modeling, simulation, and synthesis. TLM-based system-level design methodology is an approach that takes advantage of Transaction Level Modeling (TLM) library [4] in addition to the SystemC [5], which is a hardware description language for systemlevel design. In ESL design methodology, an application is specified by a task graph which represents containing tasks and their dependencies. Each task of a given application is mapped onto a processing core of the target multiprocessor systems. Network on chip (NOC) is an important architecture that is used for implementing multiprocessor systems. Different mapping alternatives constitute the design space which could be explor
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