A Scanning Tunneling Microscopy Study: Si/SiO 2 Interface Roughness Induced by Chemical Etching
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A Scanning Tunneling Microscopy Study: Si/SiO2 Interface Roughness Induced by Chemical Etching Jixin Yu1,2, Lequn Liu2, and Joseph W. Lyding2 1 Department of Electrical Engineering, USC NanoCenter, University of South Carolina, Columbia, SC 29063 2 Beckman Institute, University of Illinois, Urbana, IL 61801 ABSTRACT The Si/SiO2 interface roughness has received tremendous interest due to its relation to channel mobility degradation and dielectric reliability. We have used ultra-high vacuum scanning tunneling microscopy to directly examine the Si/SiO2 interface and study the roughening effect caused by chemical etching. The rms-roughness extracted quantitatively from the STM topography was found to be doubled from 0.111nm to 0.232nm by the normal NH4OH/H2O2 treatment, and further increased to 0.285nm for additional etching steps. It was also found that there were no regular single steps on the SiO2/Si(100) interface. INTRODUCTION With the continuous scaling down of gate dielectric thickness in deep submicron MOSFETs, the SiO2/Si(100) interface roughness (more generally, Si-gate dielectric interface roughness) becomes a crucial factor for device performance [1,2]. Interface roughness is believed to affect the inversion layer carrier mobility in high transverse effective electric fields, gate dielectric reliability, gate leakage current, ballistic transmittance, and the quality of atomic layer deposition of high-k gate dielectrics [3-8]. Several experiments have indicated that the first step of the RCA cleaning (SC-1 cleaning), which is the most commonly used cleaning procedure for Si wafer, would greatly roughen the Si surface [4,9-12]. In this paper, we use ultra-high vacuum scanning tunneling microscopy (UHVSTM) to tunnel through a 1nm-thick industry-standard oxide and directly observe the SiO2/Si(100) interface in real space, and reveal roughening effect of SC-1 and other etching/cleaning procedures. EXPERIMENT Three SiO2/Si(100) samples studied in this paper were cut from 8-inch wafers that had gone through different surface treatments before gate oxide growth. The first sample (Sample A) underwent the surface treatment involved in a conventional process flow compliant with shallow trench isolation (STI). The wafer was first cleaned using a P-clean (H2SO4/H2O2) followed by SC-1 (NH4OH/H2O2) clean with a final 50 seconds 50:1 H2O/HF dip. Subsequently, a 5-nm thick screen oxide was grown at 800 ºC and the shallow trench isolation process flow was executed. After the nitride was stripped and ion implantation (Boron dopant density approximately 1.2 ×1018cm-3), the oxide was P-cleaned and then removed with a 100% HF overetch. Finally, after executing an SC-1 clean followed by HF, the gate oxide was grown at 1000 ºC. The STM experiments were performed on gate test pattern areas. The second surface treatment (Sample B) involved the use of a P-clean followed by a minimum duration HF dip prior to oxidation to produce a 2 nm thick screen oxide at 1000 ºC. After implantation through the screen oxide, the
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