A Semi-Insulating Layer for Novel High Voltage Polysilicon Thin Film Transistors
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Source
Gate
Field Plate
Drain
Source
Gate
Silicon Oxide
Drain
Silicon Oxide
I- Channel -*I*- Offset Region -* I-
Figure 1. Metal field-plate HVTFT.
Semi-insulator
Channel -*to- Offset Region -- H
Figure 2. HVTFT with semi-insulating layer.
For c-Si device applications the SIPOS layer is typically deposited by the Low Pressure CVD technique at temperatures in the range 620'C to 660C [8]. The as-deposited films must then be annealed at temperatures in excess of 900'C [9] making them incompatible with glass based technologies. Low temperature semi-insulating films have been deposited by the PECVD technique from SiH 4 and N2 0 gas mixtures at temperatures • 350'C [10]. However, the conductivity of the PECVD films so far reported is limited to • 10-10 t- 1 cm- 1 . This is likely to be insufficient to optimise the performance of HVTFTs over a range of device structures and dimensions. Accurate and repeatable control of the semi-insulating film conductivity, over several orders of magnitude, will be required. In the present work we use device simulation to demonstrate the advantages of the S-I HVTFT structure. The optimisation of a glass compatible semi-insulating layer, suitable for HVTFT applications, is then described in detail. Helium dilution of the SiH 4 and N 2 0 reactant gases is investigated in an attempt to improve the large area uniformity and reproducibility of the PECVD semi-insulating films [11]. The effects of low temperature (• 600'C) furnace anneals on the physical and electrical properties of the PECVD semi-insulating films are also determined. DEVICE MODELLING The two dimensional simulator MEDICI 2.0 with Trapped Charge AAM was used to model device performance [12] using a simple density of states (DOS) profile for the intrinsic poly-Si layer [13]. The simulated device characteristics are critically dependent on the poly-Si DOS. However, by maintaining a constant DOS profile in all simulations, the relative merits of the different HVTFT structures were determined. The film thicknesses and device dimensions used in the simulation are listed in Table I. The metal field plate and the semi-insulating layer were assumed to be self-aligned to the edges of the gate and drain implants. The channel and offset regions were undoped. Table I. HVTFT modelling parameters. poly-Si layer thickness 0. 2 ktm gate oxide thickness 0. ijim field plate oxide thickness 0.2ktm
channel length offset length
5gtm 15gm
The potential distribution in a FP HVTFT at an applied drain voltage of 200V (gate voltage = 30V, field plate voltage = 30V) is shown in Figure 3 and illustrates the field crowding at the drain edge of the metal field plate which leads to device failure. The field distribution in the device is plotted in Figure 4. In the drain region the field exceeds 7 x 105 Vcm- 1 . The location of the high field region is dependent on the field plate potential and can occur at either the drain (low field plate voltage) or gate edge (high field plate voltage). 732
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