Polysilicon Super Thin Film Transistor Technology
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POLYSILICON SUPER THIN FILM TRANSISTOR TECHNOLOGY TAKASHI NOGUCHI, HISAO HAYASHI and TAKEFUMI OHSHIMA Research & Development Div., Semiconductor Group SONY Corp., Atsugi, Kanagawa, Japan ABSTRACT Advanced super thin(of less than 800A) polysilicon films with the grain size of more than lum were de'veloped by applying the Si + implanted amorphization and subsequent annealing. With this film, TFT with superior characteristics could have been fabricated on quartz or Si0 2 /c-Si substrate. At the process of 600 0 C, field effect electron mobility as large as 60cm 2/V.s. was obtained. Furthermore, using the high temperature process of 1000 0 C, electron and hole mobility increased to the value of 120 and 80cm2 /V.s , respectively. The values of field effect electron mobility were almost constant over a wide temperature range. The CMOS scanner was fabricated and operated faster than 5MHz. These advanced polysilicon TFT's have a great impact on large size LSI. INTRODUCTION Recently, research on amorphous- and polysilicon TFT's are very active in order to realize large size LSI on a glass such as LCD(Liquid crystal display) etc.. Polysilicon film has high carrier mobility potentially compared to a-Si:H film, but it is difficult to realize low leakage current. In order to achieve both higher mobility and lower leakage current, some important key points are considered. They are 1) Very thin polysilicon active layer 1 ,2,3) 2) Large grain size, and 3) Effective hydrogenation at the grain boundary 4,5) To realize them, Si+ implanted amorphization and low temperature annealing 6,7)8,,0 of very thin silicon film have been tried8,9,l0) SOLID PHASE GROWTH AND DEVICE FABRICATION Silicon films with the thickness of 800A or 1500A were deposited on either quartz or Si0 2 /c-Si substrate by LP-CVD method at 610 0C. Si + was implanted to bring the polysilicon films into disordered state. The ion accelerated energy was selected to be 40keV for 800A thick film and 30keV + 75keV for 1500A thick film. The ion dose was changed in the range of 1.5 x 10 to 101 cm for 800A thickness. To get large and flat grains, low temperature annealing at 600 0C in nitrogen was performed. For the conventional Mat. Res. Soc. Symp. Proc. Vol. 106,
1988 Materials Research Society
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1000C process, dry thermal oxide was formed as gate insulator, and simultaIn the neously, polysilicon film was thinned to less than 500A thickness. case of the film recrystallized with 1500A thickness, and for low temperature process, solution etching(NH4 OH + H2 0 2 +H2 0) was adopted to make the film thinner. Then, CVD SiO2 was used as gate insulator. Doped polysilicon gate was formed by diffusion of phosphorus from PSG(Phospho-silicate glass) or by ton implantation. Source and drain were formed by implantation of Phos+ or Finally, hydrogenation of annealing was done from the passiAs+ and BF2 +. vated plasma SiN:H film at 400'C. To analyze the grain growth of the films in disordered amorphous state, 11) , and optical U-V(ultra-violet) reflectance measurements at around 4.4 eV
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