High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors
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High Voltage Effects In Top Gate Amorphous Silicon Thin Film Transistors N. Tosic1, F. G. Kuper1,2 and T. Mouthaan1 University of Twente, MESA+ Institute, P.O. Box 217, 7500 AE Enschede, The Netherlands 2 Philips Semiconductors, MOS4YOU, Nijmegen, The Netherlands
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ABSTRACT In this paper, an analysis of the high voltage induced degradation in top gate amorphous silicon Thin Film Transistors (TFT) will be shown, including the aspect of self-heating. It will be shown through experimental results that the degradation level under high voltages on drain and gate is different for TFT’s with different channel lengths. In addition, the temperature distribution over the TFT area for devices with different channel length is simulated. Simulation shows that the peak of temperature distribution is located at the drain/channel edge and that level of thermal heating depends on the channel length. INTRODUCTION The degradation induced by high voltages and electrostatic discharge (ESD) is one of the most critical reasons for lower production yield in display manufacturing. In our previous work [1], considering the effect of the electrostatic discharge on a TFT, we have shown that even a low ESD zap degrades TFT's and a high ESD voltage induces electrostatic breakdown. The degradation was shown through the threshold voltage and sub threshold slope change, and it was attributed to creation of defect-states at amorphous Si /gate dielectric interface. The creation of defects was observed in the region where electrical field was higher than a critical value. It was also shown that hard breakdown is not due to this pre breakdown degradation. In addition, it was noticed that breakdown voltage depends on the channel length. However, the physical origin of this dependence between breakdown voltage and channel length was not clear and it will be considered in this paper. According to Tada et al. [2], under weak ESD whose voltage is not so high as breakdown voltage, a "soft" failure of a-Si TFT is noticed and is caused by non-adiabatic heating of the channel. In this paper, we will show that level of this thermal heating is correlated with the size of the channel length. EXPERIMENTAL Tested devices were top-gate amorphous silicon thin film transistors. A number of devices with different channel dimensions was used in the experimental. The channel width (W=100 µm) was constant, but the channel length was varied (L=4, 6, 10 and 100 µm). Series of high voltage stresses were applied in the following way: during each stress serial, the gate voltage V G was kept constant, and the drain voltage was increased from 0 to 90V with step 10V. For each drain voltage measurement was repeated 10 times, with time interval 1 s. The measurement is repeated 10 times in order to show if there is thermal degradation. Stress time was short (~ 4µs). Four serials of measurements were carried-out. In each series the gate voltage was increased.
Q8.5.1
In Fig. 1. are shown measurements of I D over time in the third series of measurements for a TFT with channel length
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