Process Degradation of a Ferroelectric Capacitor
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Process Degradation of a Ferroelectric Capacitor
Seigen Otani and Tetsuro Tamura
F project, Fujitsu Labs. Ltd. 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan Phone: +81-46-250-8231 Fax: +81-46-248-3473 e-mail: [email protected]
ABSTRACT Ferroelectrics used in a memory device such as (Pb,La)(Zr,Ti)O 3 (PLZT) are vulnerable to reducing atmosphere and lose remanent polarization easily. In the semiconductor processes, hydrogen gas is generated both from deposition gas of interlayer dielectric and from reaction between metals and moisture in the dielectric. Improving the ferroelectrics resistance to reducing environments is required for the planarization and multi-layer interconnections in future devices. Loss of remanent polarization is related to the imprint properties of the capacitor and can be improved by controlling the deposition condition of sol-gel PLZT and annealing IrO x electrode in oxygen.
INTRODUCTION
A ferroelectric random access memory or FeRAM is a non-volatile memory combining both ROM and RAM advantages. Its fast write and high write endurance as well as low power consumption make it superior to other types of non-volatile memories. As the structure of FeRAM is similar to that of DRAM, FeRAM can be fabricated basically using conventional semiconductor processes.
In the semiconductor
processes, however, the processes in a reducing atmosphere such as the deposition of inter layer dielectric(ILD) films and N 2 -H 2 anneal after the capacitor processes are used. Oxygen defects in a ferroelectric capacitor are easily generated in a reducing atmosphere. As a result, it brings about the degradation of capacitor properties such as lowering of the switching charge and the degradation of the data retention property[1-6]. Therefore, in the fabrication of the FeRAM device, it becomes an important problem to prevent the degradation of the capacitor. We present here results of the degradation of the capacitor properties caused by the ILD processes.
EXPERIMENT
The schematic cross section of the 0.5µm –FeRAM unit cell (cell size:27.3
m 2 ) is shown in Figure
1[7]. A capacitor is fabricated on top of the Si based dielectric which encapsulates the CMOS and protects
CC2.6.1
it during the fabrication of the ferroelectric film. In this work, we fabricated the ferroelectric capacitor stacks using Pt/IrO 2 electrode and PZT film deposited by a spin on conventional Sol-Gel method. The 1 st inter layer dielectric(ILD) was deposited on the capacitor, and then the contact holes were fabricated on the top electrode and the source area of the transistor. Subsequently, the PZT capacitor was annealed in an oxygen ambient in order to recover the degradation of the capacitor characteristics by the 1 st ILD. After TiN local interconnect (LI) formation, 2 nd ILD deposition, Al layer was connected to both the W-plug and the LI. After the metalization, the passivation film was deposited. The polarization-voltage hysteresis loop was measured using a Radiant Technologies RT6000S
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