A TiO $$_2$$ 2 S/D n-channel FD-SOI MOSFET-based zero capacitor random access memory device
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A TiO2 S/D n‑channel FD‑SOI MOSFET‑based zero capacitor random access memory device Dibyendu Chatterjee1 · Anil Kottantharayil1 Received: 14 March 2020 / Accepted: 23 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract We propose a parasitic BJT-based zero capacitor random access memory (Z-RAM) cell suitable for stand-alone memory applications. In this Z-RAM cell, high-bandgap TiO2 is used as the source/drain material and silicon as the channel of an n-channel fully depleted silicon-on-insulator MOSFET. Using well-calibrated TCAD simulations, we demonstrate the programming of the proposed Z-RAM cell at low drain voltages, which is a major advantage from an application perspective. At low drain voltage, hole storage is initiated by band-to-band tunnelling, which is subsequently taken over by impact ionization. Large valence band offset between TiO2 and Si ( 𝛥EV ≈ 2 eV) is utilized for storing larger number of excess holes inside the body for a longer time. This leads to the improvement of both sense margin and retention time compared to an all-silicon Z-RAM cell. We predict a retention time of 2 s and 70 ms at T = 300 K and 358 K, respectively, for device gate length of 30 nm. We have optimized the device design to obtain a write ‘0’ time of 6 μ s. Multiple non-destructive reading operation for the proposed Z-RAM cell is also demonstrated. Keywords Z-RAM · Fully depleted SOI · Parasitic BJT · Band-to-band tunnelling · Impact ionization · Titanium oxide
1 Introduction A conventional dynamic random access memory (DRAM) [1] consists of a transistor and a storage capacitor. The storage capacitor should have a minimum capacitance value of 30 fF [2] to obtain a sufficient signal-to-noise ratio. The minimum capacitance requirements are met using trench capacitor [3, 4] and stack capacitor [5, 6] technologies for sub100-nm technology nodes. In trench capacitor DRAM, after the capacitor fabrication, the capacitor dielectric has to go through the thermal budget for the remaining process steps, and also, with the technology nodes, the trench needs to be deeper to increase the electrode area, which is a challenging task [7]. For stack capacitor DRAM, once the capacitor is fabricated, they can collapse on each other during the subsequent process steps, which may shorten the metal lines, and also, the aspect ratio needs to be higher with the technology node [7]. Another big challenge for a conventional 1T-1C DRAM is the migration from 6F 2 to 4F 2 (where F is the bit * Dibyendu Chatterjee [email protected] 1
Indian Institute of Technology Bombay, Mumbai 400076, India
line half pitch) cell size. Majority of the foundries manufacture DRAM cells with 6F 2 cell size. The most recent 1T-1C DRAM (LPDDR4X) is being manufactured using ‘1y’ nm technology [8] . ‘1y’ nm is defined as 14−16 nm [9]. Gate length is approximately 20 nm [10] for ‘1y’ nm technology node chip manufactured by SAMSUNG, and this has a cell size of 6F 2 . The most promising way to increase the number of bits per
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