Advanced Ion Implantation Technology for High Performance Transistors
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Advanced Ion Implantation Technology for High Performance Transistors. Kyoichi Suguro, Atsushi Murakoshi, Toshihiko Iinuma, Haruko Akutsu, Takeshi Shibata, Yoshikazu Sugihara, and Katsuya Okumura* TOSHIBA CORPORATION Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan Phone: +81-45-770-3663, Fax: +81-45-770-3577 [email protected] ABSTRACT Cryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs.
In order to improve the precision of implanted dose, chip size implantation
technology without photoresist mask was developed.
In this technology, chip-by-chip
implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size. INTORDUCTION Defect control in shallow source/drain and the precise dose control in channel region are important issues in high performance transistors of 0.1-0.13 micron regime. With shrinkage of junction depth, the thermal budget of annealing after ion implantation becomes smaller in order to suppress impurity diffusion. On the other hand, it becomes difficult to recover the defects around deep junctions by small thermal budget annealing.
Therefore, the annihilation of defects
by annealing with small thermal budget is a key issue for 0.1-0.13 micron regime.
There are
several reports concerned with low temperature ion implantation of B, BF2 and P. [1-3]
These
papers describe that the residual defect density after furnace annealing for Si substrates implanted at low temperature is lower than that for Si substrates implanted at room temperature.
However,
complete annihilation of defects was not reported so far. We have developed a process module combined with cryo-implantation and rapid thermal annealing in order to annihilate defects in source and drain regions. [4]
J1.3.1
Another issue in doping technology is precise implantation in channel region.
In order to
improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed.
In the present technology, chip-by-chip implantation can be carried out
by a step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size [5].
In this paper, the experimental results concerned with
cryo-implantation and chip-by-chip implantation are reviewed and the some applications are presented. HOW TO DECREASE DEFECTS Figure 1 schematically illustrates primary defects and secondary defects for conventional room temperature (RT) implantation and cryo-implantation (Tsub:
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