Analysis of gate-induced drain leakage in gate-all-around nanowire transistors
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Analysis of gate‑induced drain leakage in gate‑all‑around nanowire transistors Yabin Sun1 · Yaxin Tang2 · Xiaojin Li2 · Yanling Shi2 · Teng Wang3 · Jun Xu4 · Ziyu Liu1 Received: 5 May 2020 / Accepted: 3 August 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET. Keywords Gate-induced drain leakage (GIDL) · Gate-all around (GAA) · Band-to-band tunneling (L-BTBT) · Spacer engineer
1 Introduction According to Moore’s law, power consumption will become more serious as a device continuously scales down [1, 2]. Recently, multi-gate transistors have gained much attention because of their excellent gate control ability. As one kind of multi-gate transistor, gate-all-around (GAA) nanowire transistors are regarded as promising candidates for sub-10 nm nodes [3–8]. In the GAA nanowire architecture, excellent gate control significantly reduces short-channel effects, but it also results in tight spatial proximity between the valence * Ziyu Liu [email protected] 1
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China
2
Shanghai Key Laboratory of Multidimensional Information Processing, Department of Electrical Engineering, East China Normal University, Shanghai 200241, China
3
Shanghai Institute of Space Power-Sources, Shanghai 200245, China
4
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
band of the channel and the conduction band of the drain extension [4]. Consequently, gate-induced drain leakage (GIDL) occurs, leading to higher static power consumption. GIDL in a nanoscale GAA transistor comes from the carrier tunneling under the OFF-state, and comprises transverse band-to-band tunneling (T-BTBT) and longitude band-toband tunneling (L-BTBT) [9]. T-BTBT occurs along the transverse electric field direction in the overlap region between gate and drain, and it dominants the leakage current under large negative gate bias [10]. L-BTBT is induced by band overlap of channel and the source/drain extension, a
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