Leakage and Transconductance in Polysilicon Thin Film Transistors: Effect of Grain Boundary Hydrogenation
- PDF / 308,246 Bytes
- 6 Pages / 420.48 x 639 pts Page_size
- 14 Downloads / 200 Views
LEAKAGE AND TRANSCONDUCTANCE IN POLYSILICON THIN FILM TRANSISTORS: EFFECT OF GRAIN BOUNDARY HYDROGENATION Feng Qian*, Dae M. Kim* and Galen H. Kawamoto** Department of Applied Physics and Electrical Engineering, Oregon Graduate Center, 19600 N.W. Von Neumann Drive, Beaverton, OR 97006 ** Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 *
ABSTRACT The n- and p-channel field effect transistors are fabricated in as-deposited and grain boundary passivated polysilicon thin films. The performance of these thin film transistors (TFT's) is characterized and compared. Specifically, the transconductance and leakage behavior are discussed in detail in correlation with the grain boundary properties. The I-V characteristics are modeled from a unified point of view. INTRODUCTION Polysilicon thin film transistors are increasingly applied in large area displays[I-3]. We have recently characterized both inversion-mode (n-channel) and accumulationmode (p-channel) polysilicon TFT's and modeled the device performance, using a unified formulation[4]. The model utilized the concept of effective doping and is one dimensional, analytic and in good agreement with experimental data. In this paper we further elaborate on the device transconductance and leakage behavior. Specifically, the performance of these devices is correlated with different process conditions used, in particular the grain boundary passivation. Additionally, super thin film transistors are briefly discussed. EXPERIMENT AND RESULTS The thin film transistors were fabricated as follows: A 200 nm thick silicon chanat 550'C or 620'C, followed by the nel was deposited on 600 nm thick thermal oxide 2 boron implantation with a dose of 8x 1011 cm- at 50 KeV for all the samples. The 0 gate oxide was grown in dry 02 at 900 C to a thickness ranging from 35 to 70 nm. Polysilicon gate was deposited to a thickness of 400 nm. Self-aligned source and drain 2 were implanted with arsenic (4X1015 cm- , 150 KeV) and boron (2x 1015 cm-2, 30 KeV) for n-channel and p-channel devices, respectively. The drive-in was carried out at 920°C for 60 min in oxygen, in which the low-temperature deposited amorphous channel layers were recrystallized and became polyerystalline silicon. After the2 metallization, some of the devices were implanted with H+ at a dose of lx 1016 cm- to pas10-5
1
,1 NA
t.,
10-6
W
7
3
15K1O' cm" 36.7nm 12pl,,
V 0=7V
0-
1
10-7
L
v 0 7V
3j) F7
105 5V
1Z I)
IW2jm W = 327nm t., 3 3 7 NA' I.5l0' CM0
I
z 10_9
.
z
a: 0 10-10-
10-10-
B -20
Fig.1
-15
-10
-5 0 5 GATE VOLTAGE, V
10
,5
A 20
-20
-:5
-,0
-5 0 5 GATE VOLTAGE, V
0
Transconductance (VG>O) and leakage (VG
Data Loading...
