Analytical Drain Current Modeling and Simulation of Triple Material Gate-All-Around Heterojunction TFETs Considering Dep
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HYSICS OF SEMICONDUCTOR DEVICES
Analytical Drain Current Modeling and Simulation of Triple Material Gate-All-Around Heterojunction TFETs Considering Depletion Regions C. Ushaa,* and P. Vimalaa a Department
of Electronics and Communication, Dayananda Sagar College of Engineering, Bangalore, Karnataka, India *e-mail: [email protected] Received May 11, 2020; revised July 7, 2020; accepted August 13, 2020
Abstract—This paper deals with electrostatic behavior of triple-material gate-all-around hetero-junction tunneling field-effect transistors (TMGAA-HJTFET) device. The model is advantageous in apprehending a comparative study with the single-material gate-all-around hetero-junction tunneling field-effect transistors (SMGAA-HJTFET) in terms of surface potential, electric field, drain current, transconductance, and threshold voltage. The surface-potential distribution in partition regions along the channel is solved by using two-dimensional Poisson’s equation. By using the drift and diffusion current, drain current is derived, and IOn/IOff ratio of 1011 is gained from analytical modeling and TCAD simulation. Transconductance and threshold voltage are derived from the tunneling current. The proposed model results are validated by the ATLAS TCAD simulation tool. Keywords: drain current, surface potential, electric field, TFETs, TCAD simulation DOI: 10.1134/S1063782620120398
1. INTRODUCTION Tunnel field-effect transistors (TFETs) have drawn attention of semiconductor academic researchers and industry for their loftier performance in subthreshold region. TFET devices operate based on band-to-band tunneling principle, which significantly improves the switching of On and Off states at lower voltages. Compared with the metal oxide–semiconductor fieldeffect transistor (MOSFETs), TFETs has low subthreshold swing (i.e., below 60 mV/dec), high IOn/IOff ratio, low Off-state current, low leakage power consumption, and better immunity of short-channel effects [1–3]. The On-current performance of the TFET device is low due to small tunneling efficiency of electrons in larger band gap than the conventional MOSFET devices [4]. Thus, to improve On-current performance many device models are proposed and analytically explored. Based on source, depletion charge and mobile charges are analyzed for the device double-gate TFET (DG-TFET) [5, 6]. Gate engineering with materials having different work function contributed significant control over short-channel effects, some studies dealt with dual material and triple material [7–10] in recent years. Gate-all-around nanowire TFETs lead to steeper subthreshold slope due to high-level control of gate as field lines get originated from the drain that can’t pen-
etrate into the channel, and get terminated at the gate [11, 12]. Nanowire TFETs with efficient gate along with channel engineering of different work function materials are proposed to improve the On-current performance; steep subthreshold slope, reduced DIBL, and threshold voltage roll-off [13–15]. Hetero-junction TFETs lead to inc
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