Analytical modeling of surface potential, capacitance and drain current of heterojunction TFET
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Analytical modeling of surface potential, capacitance and drain current of heterojunction TFET Sarabjeet Kaur1 · Ashish Raman1 · Rakesh Kumar Sarin1 Received: 18 July 2020 / Accepted: 27 August 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract This paper presents an analytical model for double-gate (DG) Heterojunction Tunnel Field Effect Transistor (H-TFET). The Poisson’s equation is solved to obtain the electrostatic potential solution which is used to drive the capacitance and drain current model. To include the impact of n-type impurity atoms in the channel region, Poisson’s equation considers the accumulation charges and ionized charges. Similarly, these charges are considered for capacitance modeling. Different III–V materials along with group-IV materials are being used to enhance the performance of H-TFET. The proposed model includes the impact of off-set between the bands due to the formation of heterojunction at the tunneling interface. The model also incorporates the influence of both the gate and the drain voltages, simultaneously. To ensure the performance of the developed model, the modeled results are validated with TCAD simulation results and a good match is obtained between them. In addition, the developed model does not include any implicit function making it SPICE-friendly for circuit designing. Keywords Analytical model · Drain current · III–V materials · Heterojunction tunnel field effect transistor (H-TFET), Surface potential · Terminal capacitance
1 Introduction With the increasing demand for more and more functions along with the downscaling of device size, power consumption is becoming a crucial parameter to decide the fate of up-coming device technology [1]. Devices relying on thermionic emission of electrons can offer a minimum sub-threshold swing (SS) of 60 mV/Dec at room temperature [2, 3]. Therefore, further reduction of supply voltage is not possible in MOSFETs and hence, restricting them from achieving the required demand of low power consumption in devices. Devices with steeper SS can solve the problem of power consumption, therefore, devices relying on band-toband tunneling (BTBT) mechanism can be a potential nominee for the up-coming device technology [4–6]. Tunnel field effect transistors (TFET) working on BTBT mechanism can offer SS steeper than 60 mV/Dec. Therefore, reduction in supply voltage can be achieved which leads to lower power consumption. However, lower on-current and ambipolar * Sarabjeet Kaur [email protected] 1
VLSI Design Lab, ECE Department, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, India
behaviour are the leading hindrance in the implementation of TFETs in the integrated circuits [7, 8]. Therefore, heterojunctions are being used by the researchers to enhance the on-current and to reduce the ambipolar behaviour, so that overall improvement in ION/IOFF ratio can be achieved in TFETs [9–14]. In heterojunction TFET (H-TFET), different materials are used for source and channel region [10, 11, 14]. Differe
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