Band Alignments of High-K Dielectrics on Si and Pt
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ABSTRACT Materials with a high dielectric constant (K) such as tantalum pentoxide (Ta 2O5 ) and barium strontium titanate (BST) are needed for insulators in dynamic random access memory capacitors and as gate dielectrics in future silicon devices. The band offsets of these oxides must be over I eV for both electrons and holes, to minimise leakage currents due to Schottky emission. We have calculated the band alignments of many high K materials on Si and metals using the method of charge neutrality levels. Ta 20 5 and BST have rather small conduction band offsets on Si, because the band alignments are quite asymmetric. Other wide gap materials A120 3, Y 20 3 , ZrO 2 and ZrSiO 4 are found to have offsets of over 1.5 eV for both electrons and holes, suggesting that these are preferable dielectrics. Zirconates such as BaZrO 3 have wider gaps than the titanates, but they still have rather low conduction band offsets on Si. The implications of the results for future generations of MOSFETs and DRAMS are discussed. INTRODUCTION The rapid decrease in device dimensions has led to a need for alternative, high dielectric constant (K) insulators for use instead of silicon dioxide in the storage capacitors of dynamic random access memories (DRAMs) and as the gate insulators in semiconductor field effect transistors. When silicon dioxide layers are thinner than -2 nm, the leakage current due to
Fowler-Nordheim tunnelling becomes excessive. The alternative is to use thicker layers of high K dielectrics, which have the same equivalent capacitance or equivalent oxide thickness. For DRAM, the first high K dielectric to be introduced is tantalum pentoxide [1,2] followed by barium strontium titanate (BST)[3,4]. The general requirements for the new dielectrics for MIS applications are: (I) High free energy of formation, to give themodynamic stability against reaction of the high permittivity oxide in contact with silicon. The material must withstand reducing or vacuum anneals between 800'C and 1050'C for it to directly replace silicon dioxide in MOSFETs without large changes in the existing fabrication process. Without sufficient stability, cation diffusion into the transistor gate is likely during these anneals. (2) Low diffusion coefficients for oxygen. If oxygen diffusion across the gate dielectric is too high, high temperature anneals could not be endured without forming low permittivity interfaces. For example, Ta 20 5 reacts with Si [5]. (3) Interfaces with Si provide good barriers to both electron and hole conduction. (4) The interfaces with Si must have low defect concentrations, so as not to degrade carrier mobilities by scattering. The requirements for DRAM capacitors are less onerous, as the dielectric is bounded by Pt and diffusion barriers, and is not in direct contact with silicon. However, gate dielectrics are in direct contact with the silicon channel. It is not clear that the new dielectrics can act as good conduction barriers as Si0 2, as they have much narrower band gaps than silicon dioxide. The potential barrier at
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