Bias-Temperature-Stress Induced Mobility Improvement in 4H-SiC MOSFETs

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t Rensselaer Polytechnic Institute, Troy, NY 12180-3590, U.S.A. Tel: 518-276-6044, Fax: 518-276-8761, e-mail: [email protected] : Philips Research, Briarcliff Manor NY 10510, U.S.A. ABSTRACT In this work, we report on an instability which affects the field effect mobility in 4HSiC MOSFETs. The devices (MOSFETs and capacitors) were subjected to a biastemperature stress (BTS) for 30 minutes at 150 0 C at stress voltages corresponding to oxide fields upto 1MV/cm. Following a positive BTS(i.e. gate voltage positive), the field effect mobility increased by upto two orders of magnitude from the original value; upon application of a negative BTS to the MOSFET, the device characteristics degraded to the unstressed state. The high mobility state could be recovered by a positive BTS and was reversible with repeated bias stressing. An explanation of this phenomenon is proposed based on the effect of interfacial ions on the dependence of both trapped charge and inversion charge densities on gate bias. INTRODUCTION The electrical properties of the current state-of-the-art SiC-SiO2 interfaces are inferior to those of silicon. The densities of oxide charges and interface states are much higher than those at the Si-SiO 2 interface[l]. The effect of the localized states is seen in the degradation of the transconductance and the increase in the threshold voltage of the MOSFETs[2]. The understanding and control of the characteristics of SiC-SiO2 interface is crucial to the realization of practical SiC MOS devices. In this work, we report the investigation of an instability which affects the field effect mobility in SiC MOSFETs. MOSFET FABRICATION The 4H-SiC wafers used for the fabrication of the MOSFETs had an epitaxial thickness and doping of 10 ym and 4x101' cm- 3 respectively. The wafers were cleaned before a 800nm thick plasma TEOS oxide (field oxide) was deposited on the wafers. A 100nm thick plasma TEOS oxide was deposited to act as a pad oxide during implantation of the source and drain. The source and drain were then implanted with nitrogen (80keV, 2x1015 cm-2; 40keV, 1x 10is cm- 2 ) at 650 'C. The samples were then annealed at 1200 °C for 1 hour in an argon to electrically activate the implants.

63 Mat. Res. Soc. Symp. Proc. Vol. 572 ©1999 Materials Research Society

Source and Drain Contacts Poly-Si gate

Source

SiO

Drain p-epi

p+4H-SiC Fig. 1: Schematic of the 411-SiC lateral MOSFET. After the implant activation anneal, the field oxide on one of the samples (thin oxide MOSFET) was etched back to 200nm. The samples underwent oxidation in a wet ambient at 1100°C for 6 hours and 40 min, followed by an anneal for 1 hour at the oxidation temperature in argon. The oxide was then subjected to a re-oxidation anneal in a wet ambient at 950'C for 3 hours. The annealing cycles were similar to the work by Sridevan et al [3]. Subsequent to the oxidation, polysilicon was deposited and degenerately doped by phosphorus implantation. After definition of the gate, a 600nm thick plasma TEOS oxide was deposited to serve as an inte