Enhancement Mode GaN MOSFETs on Silicon Substrates with High Field-effect Mobility
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1068-C03-02
Enhancement Mode GaN MOSFETs on Silicon Substrates with High Field-effect Mobility Hiroshi Kambayashi, Yuki Niiyama, Shinya Ootomo, Takehiko Nomura, Masayuki Iwami, Yoshihiro Satoh, Sadahiro Kato, and Seikoh Yoshida The Furukawa Electric Co., LTD., Yokohama, 220-0073, Japan ABSTRACT In this report, we have demonstrated enhancement-mode n-channel GaN MOSFETs on silicon (111) substrates. We observe a high field-effect mobility of 115 cm2/Vs, the best report for GaN MOSFET fabricated on a silicon substrate to our knowledge. The threshold voltage was estimated to be +2.7 V, and the maximum operation current was over 3.5 A. This value is the largest which have ever been reports. INTRODUCTION GaN-based devices are expected candidates for high-power switching systems since GaN has excellent figures of merit. [1] Furthermore, normally-off operation is required for fail safe operation and noise margin. Recently, normally-off AlGaN/GaN HFETs have been demonstrated by using several techniques [2]-[4]. However, these threshold voltages are below 1 V. GaN MOSFET is one of the candidates to obtain further high threshold voltage. The some groups have reported on their work of GaN MOSFETs [5]-[11]. Most of these MOSFETs have been fabricated on sapphire or GaN substrates. However, these substrates are very expensive and it is difficult to fabricate these with a large diameter. In this report, we have demonstrated enhancement-mode n-channel GaN MOSFETs on silicon (111) substrates with high field-effect mobility and a large output current operation. In order to realize a larger output current operation, we have investigated the activation annealing condition of ion implanted silicon, which was implanted into GaN to form n+ regions. EXPERIMENT Figure 1 shows the schematic cross-sectional view of the GaN MOSFET we have fabricated. A heterostructure of a 2.0 µm-thick GaN-based buffer layer and a 1.5 µm-thick GaN epilayer with Mg acceptor doping at a concentration of 1 × 1017 cm-3 was grown on a silicon (111) substrate using metal-organic chemical vapor deposition (MOCVD). Then silicon ions were implanted into GaN layer to fabricate n+ source and drain regions. The dose of implanted silicon was 3 × 1015 cm-2 with a maximum energy of 160 KeV to achieve a junction depth of 300 nm. After 500-nm-thick SiO2 deposition as a capping layer, we performed rapid thermal
annealing in an Ar ambient to activate the implanted silicon. After removing the SiO2, 60-nmthick SiO2 was deposited by plasma-enhanced chemical vapor deposition (PE-CVD) as a gate oxide, and then annealed at 800oC for 30 min in a N2 ambient. This annealing is effective to decrease the SiO2/GaN interface-state density (Dit) near the GaN conduction band [12]. Ohmic electrodes were formed by using lift-off technique of Ti/Al, and the electrodes were annealed at 600oC for 10 min in a N2 ambient. The gate electrode was also defined by lift-off of Ti/Au. The channel widths of the MOSFETs are 1.1 mm, 8.7 mm, and 16 mm with the cannel length of 4 µm. RESULTS AND DISCUSSION We
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