Characteristics of Silicon Implanted Trap Memory in Oxide-Nitride-Oxide Structure
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CHARACTERISTICS OF SILICON IMPLANTED TRAP MEMORY IN OXIDE-NITRIDE-OXIDE STRUCTURE T.S. Kalkur, Nathaniel Peachey* and Tom Moss III* Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Colorado Springs, CO 80933-7150 * Atmel Corporation Colorado Springs, CO 80906.
ABSTRACT In this work, non-volatile memory based on silicon nano trap was implemented by implanting silicon into oxide-nitride-oxide layers(ONO) on silicon. The charge storage effects in these memory structures were measured using capacitance-voltage techniques in polysilicon-ONO- silicon structures in terms of silicon implantation dose. Without silicon implantation, the devices did not the threshold shift (memory window). The memory window was found to be dependent on silicon implantation dose and DC bias (programming) voltage. The memory window did show any degradation by annealing in nitrogen or forming gas environment at 450 oC for 30 minutes. Nano trap memory elements were fabricated with 0.35 micron technology showed encouraging results up to 1e5 program/erase cylces.
INTRODUCTION Non-volatile memories based on silicon nano crystals and silicon nano traps are attracting the attention of many investigators (1-4). The nano crystal memories are expected to have long retention times, fast write times and extremely small degradation compared to conventional flash EEPROMs (3). Floating gates with nano crystals and nano traps were fabricated by silicon implantation, tin implantation, germanium implantation into silicon dioxide, silicon nano-dots self assembled by chemical vapor deposition (CVD), low pressure CVD, annealing silicon rich silicon dioxide and by high temperature oxidation of SiGe(1-8). The conventional flash technology uses oxide/nitride/oxide as the interpoly dielectrics(9). Interpoly dielectric thickness heavily influences the program erase speed, magnitude of read current, charge retention capability and other reliability issues. In this paper, we are reporting the results of nonvolatile memory characteristics of silicon implanted oxide-nitride-oxide structures on silicon.
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EXPERIMENTAL The structure of the MOS capacitors fabricated are shown in Figure 1. The thickness of LPCVD deposited oxide- nitride-oxide (ONO) was 30 oA, 190 oA and 30 oA respectively. The ONO was implanted with silicon of energy 15 KeV with dose 5E15 and 1E16 respectively at an angle of 7 degrees. The polysilicon was deposited on the ONO by LPCVD technique and it was annealed at a temperature of 950 oC for 30 minutes. The polysilicon was doped with implanted arsenic. The poly and active were silicided. In addition to the fabrication of MIS structure, flash cells with channel length 0.525 µm and width 0.805 µm were also fabricated in order to evaluate the memory characteristics. Poly
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