Negative Differential Resistance Characteristics of Silicon Nanocrystal Memory
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Negative Differential Resistance Characteristics of Silicon Nanocrystal Memory Seung Jae Baik* and Koeng Su Lim Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, 373-1, Kusong-dong, Yusong-gu, Taejon 305-701, Korea *also with Samsung Electronics co. ABSTRACT Two-dimensional (2D) Si quantum dot array was fabricated by oxidation of microcrystalline Si film deposited by photo chemical vapor deposition (photo-CVD). Average size of Si quantum dot was estimated to be 2.4nm and dot density 7 ~ 8 1011 cm-2. Nanocrystal memory device with this 2D quantum dot array demonstrated negative differential resistance characteristics and single charge tunneling phenomena, which was observed as stepwise decrease of gate transconductance. Interface states at the oxidized surface of quantum dots were assumed to explain temperature dependence characteristics. This new process is adequate for functional device application of nanocrystal metal-oxide-semiconductor (MOS) memory. INTRODUCTION Single electron memory is believed to be a substitute for current semiconductor memory in future for its low power consumption and high functionality [1-3]. To realize the concept of single electron memory, several schemes have been presented. Among them, on the viewpoint of voltage sensing, floating dot memory scheme is most feasible [4,5]. There are several types of floating dot memory [4-9]. Memory structure called nanocrystal memory or metal-oxidesemiconductor memory based on nanocrystal [6], is one of floating dot memory structure that resembles flash EEPROM (Electrically Erasable and Programmable Memory). It uses twodimensional (2D) quantum dot array as a floating gate material. As a 2D quantum dot array forming technology, self-assembled deposition [10] is well-known. We tried a different process, oxidation of microcrystalline silicon film. The feature of this method is as follows. First, the quantum dot floating gate and the control gate oxide is formed at once, and thus the interface between quantum dots and control gate oxide is relatively smoother than conventional deposited oxide film. This results in much different characteristics with conventional nanocrystal memory having deposited control gate oxide film [6,10,12]. Moreover, dot size and density can be A14.5.1
controlled by adjusting thickness or quality of as-deposited film and by regulating subsequent oxidation procedure. EXPERIMENT Before depositing µc-Si film, thin (~ 2nm) tunneling oxide was formed. Then, µc-Si film was deposited by photo chemical vapor deposition (photo-CVD). Photo-CVD has fine deposition-rate controllability thus this is quite appropriate for nanoscale thickness film deposition apparatus [11]. Because the as-deposited film has large amount of hydrogen, it would destroy the film structure at high temperature process such as oxidation. Thus dehydrogenation process was followed in N2 atmosphere at 400 ~ 430 . And oxidation process was followed at 900 for 30 minutes. We used standard metal-oxide-semico
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