Characterization and Application of Laser Induced Seeded-Lateral Epitaxial Si Layers On SiO 2
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CHARACTERIZATION AND APPLICATION OF LASER TNDUCED SEEDED-LATERAL EPITAXTAL Si LAYERS ON SiO2 M.MIYAO, M.OHKURA, T.WARABISAKO and T.TOKUYAMA Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan
ABSTRACT Electrical and crystal properties of seeded lateral epitaxial Si are evaluated as a function of distance from seeding area with the aid of a micro-probe RHEED and MOSFET fabrication. The results indicate that the quality of a grown layer is as good as that of bulk Si crystal for most of the epitaxial layer. However, at the SiO edge, electrical properties are somewhat poor due to the existence of dislocation and residual stress. Element devices useful for SOI structures are fabricated. Electrical properties of MOSPET's with double active areas indicate that surface and bottom regions of the epitaxial layer are all of device worthy quality. Insulated control gate bipolar type transistors are proposed and some preliminary results are shown. INTRODUCTION Silicon on an insulating substrate (SOT) [1,2,3] is a very attractive material structure for future VLSI. Moreover, it is raising expectations of achieving three dimensional devices and circuits. The various techniques which realize SOI structures reported to date are summarized in table 1. Techniques shown in categories (A) and (B) can be realized using a conventional oven or strip heater as a heating tool. These techniques can provide large SOT crystals, especially good crystal quality
was achieved in technique (B). However, the high temperature heating (1000 C or more) required in these processes would degrade any circuits that might be included in the substrate, when so called three dimensional devices are considered. On the other hand, localized heating techniques using a laser or electron beam, which are of recent interest, can complete the process at less than 500 C substrate temperature. However, the techniques shown in category (C) only resulted in large grain poly.Si films. The crystal is far from LSI application quality, though grain growth on the transparent substrate showed some potential for flat panel display driver circuits. Consequently, a new, low temperature SOT process with good crystal quality, is needed for three dimensional integrated device fabrication. The key factor is obviously to control the crystal orientation of the grown layer. This is because, many process parameters, i.e. etching speed, oxidation rate, impurity diffusion coefficient are strongly dependent on crystal orientation. Moreover, variation in such electronic properties as carrier mobility and MOS interface properties that originate in the different orientations of the crystal grains in which each elementary device is located, degrade total LSI characteristics.
However,
large
area
SOT
crystals
will
not
always be necessary for
circuits with high packing density. This is because the active area of elemental devices has become smaller in recent years. The essential thing is how to fabricate SOT crystals of excellent quality at desired positions. These req
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