Characterization of Arsenic Implanted Epitaxially Aligned Polysilicon-on-Silicon Films
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CHARACTERIZATION OF ARSENIC IMPLANTED EPITAXIALLY ALIGNED POLYSILICON-ON-SILICON FILMS J.L. Hoyt,E.F. Crabb6, R.F.W. Pease, and J.F. Gibbons Stanford Electronics Laboratories, Stanford, CA 94305 ABSTRACT Nonuniformities in the polysilicon-to-silicon interface and in the polysilicon structure are expected to produce a nonuniform diffusion front when arsenic is diffused from polysilicon during epitaxial alignment. Using transmission electron microscopy, we find surprisingly uniform arsenic diffusion fronts in the underlying silicon substrate following high temperature annealing. Several explanations of this result are proposed. We also report new evidence of a strong reduction in the time to achieve complete epitaxial transformation of the polysilicon when the polysilicon thickness is reduced. A corresponding reduction in the associated arsenic penetration depth is demonstrated. INTRODUCTION Polysilicon films formed by a low pressure chemical vapor deposition (LPCVD) process are used extensively for self-aligned contact formation in bipolar transistors. For the emitter contact, polysilicon is deposited directly on the silicon substrate and implanted with arsenic. A high temperature anneal is used to outdiffuse the arsenic from the polysilicon into the substrate to form the active emitter region. The standard LPCVD process inevitably produces a thin, thermally unstable interfacial layer at the polysilicon-to-silicon interface [1,2]. Because the break-up of this interfacial layer and concomitant epitaxial regrowth of the polysilicon with respect to the substrate is difficult to control, large variations in transistor base current and emitter resistance can result from furnace annealing in the 800 to 1000 'C temperature range [3,4]. A short, high-temperature emitter drive-in which completely breaks-up the interfacial layer and transforms the polysilicon into epitaxial silicon has been proposed to alleviate this process sensitivity. Alignment of arsenic implanted emitters has been realized in high-frequency devices using fast furnace annealing at 1150 'C [5]. Bipolar transistors fabricated with high emitter arsenic concentrations 3 (> 5 x 1020 cm- ) and high-temperature Rapid Thermal Annealing (RTA) show little sensitivity of base current to residual defects in the aligned polysilicon, while retaining advantages over metal-contacted emitters [6]. An added benefit of the high temperature RTA is reduced base and emitter resistance [7]. For undoped polysilicon-on-silicon, alignment is observed to proceed from the polysilicon/single crystal interface, where epitaxial columns form in certain regions, and grow towards the surface [8]. The time to induce complete epitaxial transformation ("complete coalescence") is reduced dramatically when the average arsenic concentration in the polysilicon is increased from 1020 to 1021 cm-3[9,10]. In previous work, we show that RTA at high temperatures is advantageous for inducing complete coalescence while minimizing arsenic diffusion into the substrate [11]. Two key questions concerning e
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