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ELECTRICAL ACTIVATION OF HEAVILY DOPED ARSENIC IMPLANTED SILICON J. SAID*, H. JAOUEN*, G. GHIBAUDO*, I. STOEMENOS** P. ZAUMSEIL*** *Laboratoire de Physique des Composants & Semiconducteurs, ENSERG, 23 Rue des Martyrs, B.P. 257, 38016 Grenoble Cedex, France **Department of Physics, University of Thessaloniki, Thessaloniki, Greece ***Akademie der Wissenchaften der DDR, Institut fur Halbeiterphysik, Frankfurt, Krosingstr 2, 1200-Frankfurt, GDR ABSTRACT The combination of electrical, Transmission Electron Microscopy and Triple Crystal X-ray Diffraction measurements allow us to separate the existence of a local impurity activation process from the amorphous- crystal transformation. The local process occurs in the highly damaged surface layer induced by the arsenic implantation and is efficient well below the Solid Phase Epitaxy transition temperature. It is suggested that point defect migration should play an important role in the electrical impurity activation at low annealing temperatures. 1- INTRODUCTION The understanding of the annihilation process of implantation induced defects has been the subject of much studies during the last years. However, a certain confusion still remains about the mechanisms by which the impurities are electrically activated and the surface layer reconstructed. In this work, we investigate separately the role of the impurity activation and the recrystallization processes by combining Spreading Resistance, Triple crystal X-ray diffraction (TCD) and Transmission Electron Microscopy (TEM) measurements. Such a combination of electrical and physical characterizations should yield a better insight in the defect annihilation process in highly doped silicon. 2-

EXPERIMENTAL DETAILS

Samples were realized on P type silicon wafers with

crystal orientation and 3.9 Q.cm substrate resistivity. Prior to implantation, the wafers were provided with a 40 nm thick SiO thermally grown passivating layer. Arsenic ions of 150-200 keV were then implanted, at room temperature, in the dose range 1013-1015 cm2-. After implantation the silicon samples were subsequently thermally annealed under a dry nitrogen ambient for various temperatures (200°C-1100°C) and various durations. The Spreading Resistance measurements were carried out using a Solid State Measurements system (ASR-100B). The resistivity profiles of the implanted layers were deduced from the gross Spreading Resistance curves by applying the

Mat. Res. Soc. Symp. Proc. Vol. 128. c 1989 Materials Research Society

600

Local Slope Approximation of the addition, the samples were analyzed to determine the spatial extension and the amorphous layer thickness silicon sample both before and after

Dickey model [1]. In by TEM and TCD in order of the defected region at the surface of the thermal annealing.

3- RESULTS AND DISCUSSION Fig.l shows the thermal annealing effect on the 4 resistivity profile for a N+/P sample implanted at 2xl0• 2 cm- . After annealing, the surface resistivity of a low temperature annealed sample (400°C, lh) drops by more than 7 decades