Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technol
- PDF / 2,769,541 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 18 Downloads / 196 Views
D5.4.1
Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technology Chungho Lee, Udayan Ganguly and Edwin C. Kan School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A. ABSTRACT Experimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit selfassembly process could be successfully adapted beyond 90nm metal nanocrystal memory technology with satisfactory parametric yield in the nanocrystal number density. INTRODUCTION Fluctuation on the number of nanocrystals in a small MOS gate area poses one of the main bottlenecks for the scalability of nanocrystal-based nonvolatile memories [1-3] beyond 90nm CMOS technology. For the standard gate-first process [7], if the nanocrystal formation or deposition is done before the gate stack patterning with self-aligned source/drain implantation, there needs to be at least 100 nanocrystals within the effective gate area to control the number fluctuation below 10% according to the nonconstrained ideal Poisson distribution. For a typical 3-4nm nanocrystal diameter and spacing, the effective gate area will be larger than 80nm×80nm in order to satisfy the parametric yield requirements. In the device fabrication aspect, the gate first process also has a disadvantage of the subsequent thermal treatment restriction, because of possible metal contamination to the channel from nanocrystals during the high temperature annealing for dopant activation. The serious contamination by Pt nanocrystals was observed after ~900°C 10sec annealing [6]. This number fluctuation in gate area scaling and the thermal budget problems can be much alleviated by the gate-last process [4,7,8] where nanocrystal self-assembly is performed after the S/D formation and the gate patterning. Self-alignment of source and drain can still be achieved through a dummy gate replacement, which is the so-called damascene- or replacement-gate process [7]. Phosphosilicate glass (PSG) diffusion without a gate replacement can be another alternative [4]. Furthermore, due to the additional surfaces at the sidewalls and corners in the effective gate area seen by the metal atoms, physical se
