Eluding Metal Contamination in CMOS Front-End Fabrication by Nanocrystal Formation Process
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Eluding Metal Contamination in CMOS Front-End Fabrication by Nanocrystal Formation Process
Zengtao Liu, Chungho Lee, Gen Pei, Venkat Narayanan and Edwin C. Kan School of Electrical and Computer Engineering, Cornell University Ithaca, NY 14850
ABSTRACT A technique to form metal nanocrystals on silicon or thin SiO2 film by Rapid Thermal Annealing (RTA) of thin metal film is developed and integrated into standard CMOS processing to make EEPROM devices and improve metal-semiconductor contact resistance. I-V and C-V measurements are carried out on MOSFETs and MOS capacitors containing Au, Ag, Pt, and Si nanocrystals as floating gate for universal mobility and minority carrier lifetime extraction. Mobility around 300 cm2/V-sec and minority carrier lifetime within 0.02 ~ 0.1 µsec are observed for all cases including the control samples that do not go through the metal nanocrystal formation process, which suggests that the substrate is virtually free from metal contamination. Using this technique, thicker metal film can potentially be achieved as well by stitching thin metal layers on top of the nanocrystals.
INTRODUCTION Use of metals in nano-scale CMOS structures offers many attractive device features. Conventional CMOS uses channel doping as a means for threshold voltage adjustment and the control of short channel effect. However, as the devices scale into nanometer regime, the random position/number distribution of the channel dopants introduces large fluctuations in the threshold voltage [1]. Metal gate can alleviate this problem by providing threshold voltage adjustment through the design choice of work function, with extra benefits of eliminating poly depletion and dopant penetration [2]. Metal gate with mid-gap work function is also a necessity for fully depleted ultra-thin SOI devices because of their threshold insensitivity to channel doping [3]. Metal nanocrystal floating gate EEPROM cells are much less subject to interface states and offer lower voltage/longer retention operations than Si/Ge nanocrystal ones [4]. Metal source/drain contacts by thin films [5] or nanocrystals [6] can reduce the sheet/contact resistance in Schottkybarrier MOSFET [7] and potentially eliminate the need of doping entirely in CMOS. However, Metals are conventionally forbidden in the front-end fabrication before the relatively thick CVD oxide (>100nm) is deposited over poly gate layers, especially for shortchannel and shallow-junction devices. Metals can contaminate oxide and Si by junction spiking, grain boundary worming, mismatched expansion and deep diffusion during later thermal cycle, which can cause serious hazard to channel mobility, minority lifetime, interface states and oxide quality [8]. In the present study, we have found that if metals are introduced as ultra-thin films (
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