Annealing effects on Si nanocrystal nonvolatile memories
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Annealing effects on Si nanocrystal nonvolatile memories Panagiotis Dimitrakis1, C. Bonafos2, S. Schamm-Chardon2, G. Ben Assayag2, P. Normand1 Institute of Microelectronics, NCSR “Demokritos”, 15310 Aghia Paraskevi, Greece 2 CEMES-CNRS, Université de Toulouse, nMat group, BP 94347, 31055 Toulouse cedex 4, France 1
ABSTRACT The effect of thermal treatments in oxidizing ambient on the structural and electrical properties of low-energy Si-implanted thin SiO2 layers which previously subjected or not to high temperature annealing in inert ambient was investigated. Based on TEM examination, charge trapping evaluation and FN conduction analysis of the resulting Si-NC SiO2 matrices, a model taking into account the healing of excess silicon atoms introduced by implantation and the generation of Si interstitials by oxidation above and below the viscoelastic temperature of SiO2 is proposed. INTRODUCTION The nanocrystal (NC) nonvolatile memory (NVM) devices are potential candidates for replacing the conventional polysilicon floating gate memories at technology nodes below 45nm [1]. Nanocrystals of a large number of materials have been investigated in order to optimize the operation conditions, the performance and the reliability of NC-NVMs. A significant amount of research has been carried out utilizing semiconducting NCs, like Si and Ge. The Si-NCs seem to meet most of the processing integration requirements for future manufacturing in a CMOS environment [2]. A promising technique to realize self-organized Si-NCs into thin tunnel oxide layers is the ultra-low-energy ion-beam-synthesis (ULE-IBS) that basically comprises the steps of ion implantation at an energy ≤1keV and subsequent annealing [3,4]. ULE-IBS of Si-NCs is of special interest due to its inherent compatibility with CMOS processing. Attractive device results have been presented using such a technique demonstrating low-voltage operation at reasonable speeds, endurance to repeated write/erase cycles and 10-year data retention. [5]. Different experiments revealed that in addition to the ion-implantation parameters [9], the postimplantation annealing conditions play a key role on the operation and performance of Si-NCNVMs [6-8]. Among the different annealing atmospheres that have been tested, annealing in presence of a small percentage of oxygen has been proved to be a useful method to control the size and the density of Si-NCs as well as to improve the integrity of the implanted oxide. Although, the effect of oxidation on Si-NCs has been studied and modeled thoroughly [10], it is not well understood how oxygen affects the memory performance. In this paper, we present structural and electrical studies conducted on oxygen-annealed Si-implanted thin SiO2 layers, which previously suffered or not high temperature annealing in inert ambient. More specifically, we investigate the effect of annealing time in oxidizing ambient on the SiO2 regions located above and below the NCs layer, which are commonly referred to as the control (CO) and tunnel (TO) oxides respec
