Degradation Study of Ultra-thin JVD Silicon Nitride Mnsfets
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Degradation Study of Ultra-thin JVD Silicon Nitride MNSFETs K. N. ManjulaRani, V. Ramgopal Rao and J. Vasi Department of Electrical Engineering Indian Institute of Technology, Bombay Mumbai 400076 INDIA email: rani,rrao,[email protected]
Abstract In this paper we discuss a new method for measuring border trap density (N ) in sub-micron transistors using the hysteresis in the drain current. We have used this method to measure N in Jet Vapour Deposited (JVD) Silicon Nitride transistors (MNSFETs). We have extended this method to measure the energy and spatial distribution of border traps in these devices. The transient drain current varies linearly with logarthmic time. This suggests that tunneling is the dominant charge exchange mechanism of border traps. The pre-stress energy distribution is uniform whereas poststress energy distribution shows a peak near the midgap.
Introduction Jet Vapour Deposited (JVD) silicon nitride has emerged as a possible replacement for conventional silicon dioxide MOSFETs as the gate oxide thickness shrinks [1], [2]. However the interface properties of JVD silicon nitride with silicon especially border traps have not been studied in detail. Border traps [3] or slow traps are traps existing in the dielectric of a MOS structure which can communicate with the silicon by exchanging carriers from and to the silicon bands. To measure the border trap density using the variable frequency charge pumping method [4] or gate current transient method [5], we need large-area, low-leakage devices. The capacitance hysteresis method [6], [7] needs large-area capacitors. Ultrathin high-K dielectric films deposited on silicon contain high trap density. Hence we need a method especially suited to characterize border traps in these devices. We have developed such a method using the hysteresis in the drain current.
Devices We have used JVD silicon nitride n-channel transistors (MNSFETs) and conventional silicon dioxide n-channel devices (MOSFETs) in this experiment with a substrate doping concentration of 1 10 cm . The gate dielectric thickness for the JVD nitride devices is 3.1nm (EOT). The MOSFETs have a gate oxide thickness of 3.9nm. Both set of devices were fabricated at UCLA except the JVD deposition which was done at Yale University. The channel lengths of devices are 0.2, 0.25, 0.28, 1 and 10 m. The channel width is 10 m.
Measurement Technique During the measurement of hysteresis in the drain current, the transistor is biased in linear region with a V of 0.1V. The measurement starts by setting V = -2.5V biasing the device in accumulation. The gate voltage is swept from accumulation to inversion (forward I -V ) and from inversion to accumulation (reverse I -V ). In inversion, V is set to 1.5V. The gate bias is stepped at the rate of of 50mV/second. The wait time in accumulation and inversion is 120 seconds. We have used Keithley Model 617 electrometer to measure the drain current, Keithley 2400 Source Measure Unit and HP6622A to supply V and V respectively. The magnit
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