Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics
- PDF / 145,265 Bytes
- 6 Pages / 595 x 842 pts (A4) Page_size
- 4 Downloads / 225 Views
Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics Yatin Mutha, K.N.ManjulaRani, Rakesh Lal, and V.Ramgopal Rao Department of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai-400 076, India.
ABSTRACT We have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model. INTRODUCTION For a long time now, the degradation of the gate dielectric with high field stress has been an area of active interest. Many models have been proposed to explain the degradation processes in various dielectrics. The degradation of silicon dioxide with DC stress is normally explained using the trapped-hole recombination (THR) [1] and the hydrogen transport (HT) [2] models. However, there still is debate about the dominant physical mechanism responsible for degradation of thin silicon dioxide and the nitrides and oxy-nitrides that are now promising. There is also considerable recent concern and interest on the AC degradation processes in ultra thin MOS gate dielectrics. No model proposed so far can consistently explain the degradation under different AC stress conditions in thin dielectrics. The aim of this study is to investigate the device degradation mechanisms in sub-micron MOSFETs with different bipolar stress conditions. Systematic characterize-stress-characterize measurements were used to probe degradation with various stress conditions. In this paper we focus mainly on interface degradation mechanisms in ultra-thin gate oxides with different alternating stress conditions, and our results indicate interesting physical processes identifiable through the experimental trends. EXPERIMENTS High field stress experiments were performed on JVD [3]-[6] nitride n-MNSFETs and conventional dry oxide n-MOSFETs. The nitride and oxide transistors were fabricated using identical process flow except for the gate dielectric deposition. Silicon B7.22.1 Downloaded from https://www.cambridge.org/core. University of Texas Libraries, on 29 May 2020 at 23:42:46, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/PROC-716-B7.22
nitride was deposited using the jet va
Data Loading...
