Deposition of Low-Stress Encapsulants on InP and GaAs
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DEPOSITION OF LOW-STRESS ENCAPSULANTS ON InP AND GaAs U. K. CHAKRABARTI, S. J. PEARTON, H. BARZ, A. R. VONNEIDA, K. T. SHORT AND J. W. LEE AT&T Bell Laboratories, Murray Hill, New Jersey 07974 ABSTRACT AIN deposited by D.C. triode sputtering and spin-on, phosphorus-doped glass (PSG) layers on GaAs and InP were investigated as encapsulants. These films have similar expansion coefficients to both GaAs and InP, minimizing the amount of strain induced in the near-surface region of the underlying wafer. We have quantified this effect by direct measurements of the stress in the films and by using secondary ion mass spectrometry profiling to measure the redistribution of Cr and Fe in encapsulated GaAs and InP respectively during high temperature processing. The dopant redistribution is considerably less for the AtN and PSG films compared to the more conventional Si0 2 and Si 3N 4 layers. The interaction of the films with the substrate at elevated temperatures is minimal as determined by Auger profiling and the electrical properties of the surface after removal of the encapsulants. The composition of the films remains essentially constant after annealing, as measured by Rutherford backscattering, and the thickness uniformity over large wafer diameters (2") can be excellent with close control of the deposition parameters. The activation characteristics of low dose, Si-implanted layers in GaAs using either PSG or AIN are comparable to those obtained using capless annealing or Si0 2 or Si3 N 4 encapsulation.
Introduction The recent increased interest in the fabrication of high speed, III-V based integrated circuits using an implantation-based, planar technology has focused attention on the problems associated with high temperature processing of InP and GaAs. As is well-known, incongruent evaporation of P and As occurs in these materials at temperatures below that required to activate the implanted layer. The two methods commonly used to prevent dissociation of the surface are the provision of an overpressure of the volatile element, or the deposition of a dielectric film which is a barrier to outdiffusion of both lattice constituents. The first method, commonly referred to as capless annealing, has a number of different manifestations. All of these, however, have attendant problems, including contamination of the surface by impurities in the gaseous atmosphere, or microscratches caused by movement of the wafers against each other in the proximity method of annealing. The use of an encapsulating layer removes these problems but introduces other difficulties such as strain induced in the near-surface region during annealing by the differing expansion coefficients of the cap and the substrate, reaction of the two materials, or the diffusion of impurities from the incapsulant into the substrate. [1 -41 The two most commonly used encapsulating layers for III-V materials are SiO 2 and silicon nitride, which in its stoichiometric form is Si 3 N 4 . However, it can exist in a wide variety of compositions depending on the deposition
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