Design and Analysis of a Dual-Metal-Implanted Triple-Material Cylindrical Gate-All-Around Nanowire FET with Negative Dif
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https://doi.org/10.1007/s11664-020-08572-2 Ó 2020 The Minerals, Metals & Materials Society
ORIGINAL RESEARCH ARTICLE
Design and Analysis of a Dual-Metal-Implanted Triple-Material Cylindrical Gate-All-Around Nanowire FET with Negative Differential Resistance and Negative Transconductance Behaviors SADRA SADEGHPOOR AJIBISHEH,1,2 SEYED ALI SEDIGH ZIABARI,1,3 and AZADEH KIANI-SARKALEH1,4 1.—Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran. 2.—e-mail: [email protected]. 3.—e-mail: [email protected]. 4.—e-mail: [email protected]
In this paper, we introduce three new structures of a cylindrical gate-allaround nanowire (NW) field-effect transistor (FET) to achieve negative differential resistance (NDR) and negative transconductance (NTC) behaviors. In the first structure, only one metal is implanted in the channel near the drain of the dual-material cylindrical gate-all-around NWFET based on the energy band profile modulation to obtain the NDR behavior. To achieve NTC behavior, another metal is implanted in the channel near the source; therefore, the second structure has both the NDR and NTC behaviors. In the final structure, the use of a triple-metal gate is proposed to improve the peak-tovalley current ratio. The NTC behavior occurs when the increase in VGS creates a positive lateral electric field in the channel, which causes the potential barrier tunneling (PBT) to decrease. The cause of the positive electric field formation is the cavity in the channel’s potential barrier due to implanted metals. Furthermore, by increasing VDS, the high electron scattering caused by the high electric field at the beginning of the drain region is increased and causes the electron drift velocity and IDS to decrease. Consequently, the NDR behavior is achieved. The structures are carefully simulated using numerical simulation based on non-local tunneling, and also the transfer characteristics (IDS VGS) and the output characteristics (IDS VDS) are attentively analyzed and examined. Key words: Negative differential resistance, negative transconductance, metal-implanted, non-local tunneling, triple-metal gate, gate-all-around nanowire field effect transistor
INTRODUCTION A conventional field-effect transistor (FET) provides two (on/off) states depending on their gate voltage in digital applications. When the gate-tosource voltage (VGS) is less than the threshold voltage (Vth), the FET is off, and when it is above
(Received March 13, 2020; accepted October 17, 2020)
Vth, the FET is on. For this reason, they are only suitable for binary logic in digital applications. In addition to binary logic, there is a multilevel logic that requires more than two states that cannot be implemented by conventional FETs. Furthermore, in analog applications such as oscillators and amplifiers, there is a need for negative-slope devices and their current–voltage characteristics that conventional FETs cannot provide. Devices with negative differential resistance (NDR) and negative t
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