Design Concepts for a Virtualizable Embedded MPSoC Architecture Enab
Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concept
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Alexander Biedermann
Design Concepts for a Virtualizable Embedded MPSoC Architecture Enabling Virtualization in Embedded Multi-Processor Systems
Alexander Biedermann Darmstadt, Germany Technische Universität Darmstadt, 2014 Darmstädter Dissertation, D17
ISBN 978-3-658-08046-4 ISBN 978-3-658-08047-1 (eBook) DOI 10.1007/978-3-658-08047-1 Library of Congress Control Number: 2014954234 Springer Vieweg © Springer Fachmedien Wiesbaden 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer Vieweg is a brand of Springer Fachmedien Wiesbaden Springer Fachmedien Wiesbaden is part of Springer Science+Business Media (www.springer.com)
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Abstract In the present work, a generic hardware-based virtualization architecture is introduced. The proposed virtualization concept transforms an array of off-the-shelf embedded processors into a system with high execution dynamism. At any point in time, tasks may be shifted among the processor array transparently. Neither the software of tasks nor the processor cores have to be modified in order to enable this feature. The work details task-processor interconnection, virtualized task communication as well as means for energy awareness and fault tolerance in a virtualizable MPSoC. Based on this architecture, concepts for the design of embedded multi-processor systems with the ability for a dynamic reshaping of their initial configuration are highlighted. This includes energy aware systems, fault tolerant systems as well as parallelized systems. For the latter, the so-called Agile Processing scheme is introduced, which enables a seamless transition between sequential and parallel execution schemes of tasks. The design of virtualizable systems is furthermore aided by a dedicated design framework, which integrates into existing, commercial design flows. Application examples taken from different domains in embedded system design feature specific optimization goals and demonstrate the feasibility of the
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