A Consistent Design Methodology for Wireless Embedded Systems
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Consistent Design Methodology for Wireless Embedded Systems P. Belanovi´c Institute for Communications and RF Engineering, Vienna University of Technology, Gusshausstrasse 25/389, 1040 Vienna, Austria Email: [email protected]
B. Knerr Institute for Communications and RF Engineering, Vienna University of Technology, Gusshausstrasse 25/389, 1040 Vienna, Austria Email: [email protected]
M. Holzer Institute for Communications and RF Engineering, Vienna University of Technology, Gusshausstrasse 25/389, 1040 Vienna, Austria Email: [email protected]
G. Sauzon Infineon Technologies, St.-Martin-Strasse 53, 81669 Munich, Germany Email: [email protected]
M. Rupp Institute for Communications and RF Engineering, Vienna University of Technology, Gusshausstrasse 25/389, 1040 Vienna, Austria Email: [email protected] Received 29 January 2004; Revised 15 February 2005 Complexity demand of modern communication systems, particularly in the wireless domain, grows at an astounding rate, a rate so high that the available complexity and even worse the design productivity required to convert algorithms into silicon are left far behind. This effect is commonly referred to as the design productivity crisis or simply the design gap. Since the design gap is predicted to widen every year, it is of utmost importance to look closer at the design flow of such communication systems in order to find improvements. While various ideas for speeding up designs have been proposed, very few have found their path into existing EDA products. This paper presents requirements for such tools and shows how an open design environment offers a solution to integrate existing EDA tools, allowing for a consistent design flow, considerably speeding up design times. Keywords and phrases: single system description, virtual prototyping, system on chip, automatic verification.
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INTRODUCTION
Complexity of modern communication systems, particularly in the wireless domain, grows at an astounding rate. This rate is so high that the demand of algorithmic complexity now significantly outpaces the growth in available complexity of underlying silicon implementations, which proceeds This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
according to the famous Moore’s law [1], that is, available complexity doubles every 16 to 18 months. Furthermore, algorithmic complexity even more rapidly outpaces design productivity, expressed as the average number of transistors designed per staff/month [2, 3, 4]. In other words, current approaches to wireless embedded systems design are proving inadequate in the struggle to keep up with system complexity. This problem, first introduced as design productivity crisis in 1999 by Sematech (www.sematech.org), is nowadays well known under the name the productivity gap or design gap.
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