SDMPSoC: Software-Defined MPSoC for FPGAs
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SDMPSoC: Software-Defined MPSoC for FPGAs 2 ¨ Jens Rettkowski1 · Diana Gohringer
Received: 10 October 2018 / Revised: 13 March 2019 / Accepted: 19 June 2019 © Springer Science+Business Media, LLC, part of Springer Nature 2019
Abstract Nowadays, heterogeneous Multiprocessor Systems-on-Chip are often used for a wide variety of applications such as image and signal processing due to the high computational power. However, the programming and designing of such systems requires a high expertise in hardware as well as software. This is in contrast to a short time-to-market which is essential for the industry. As a result, a crucial software productivity gap emerges. This work presents SDMPSoC which is an automatic development environment for heterogeneous and FPGA-based MPSoCs. Based on an MPI program, a heterogeneous MPSoC for FPGAs consisting of an arbitrary number of MicroBlaze processors and hardware modules is generated. Each process of the MPI program is executed by a MicroBlaze processor or a hardware module which can be selected using constraints. Furthermore, every MicroBlaze processor can be optimized by hardware modules that executes applicationspecific operations. All hardware modules can be easily programmed in the MPI program and are synthesized using high-level synthesis. Functions of the MPI program can be selected by pragmas for hardware modules that are connected to a MicroBlaze processor. A process of the MPI program can be selected by constraints for a hardware module that is a PE without MicroBlaze processor. To evaluate the environment in terms of scalability, performance and area, several use cases have been implemented on a Xilinx Zynq SoC. The development phase and programming of heterogeneous MPSoCs are significantly simplified by the automatic development environment. Keywords Software-defined MPSoC · Vivado HLS · FPGA · MPSoC
1 Introduction A current trend in the semiconductor industry is the use of heterogeneous Multiprocessor Systems-on-Chip (MPSoCs) instead of scalar systems for parallelizable tasks. This is due to the fact that heterogeneous MPSoCs provide a high efficiency in performance related to energy, since they combine the computational power of different and multiple processing elements (PEs). However, the increasing number of PEs led to high communication requirements that demand for an interconnection architecture that can cope with these Jens Rettkowski
[email protected] Diana G¨ohringer [email protected] 1
Embedded Systems of Information Technology (ESIT), Ruhr-University Bochum, Bochum, Germany
2
Adaptive Dynamic Systems (ADS), Technische Universit¨at Dresden, Dresden, Germany
high requirements. Networks-on-Chip (NoCs) are the most promising communication infrastructure for MPSoCs due to their high scalability. They scale down the concept of networks to an on-chip approach satisfying the communication demands for Systems-on-Chip (SoCs). Nowadays, complete heterogeneous MPSoCs [1, 2] can be implemented in ASICs as well as in a single FPGA. An FPGA prov
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