Die Attach Adhesion and Void Formation at the Gaas Substrate Interface
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ABSTRAC(T A model is constructed to consider the stresses (analytically and "with Finite Eý,lement Analysis (l1EA)) which result from the thermal mismatch between the die and the substrate. IA is used to simulate thermal stresses induced from temperature cycling with voids and without voids in the die-attach at the die-substrate interlace. LA)cal stress concenlration caused by voids is found to be dependent on the localion of the voids. 'the presence of an edge void at the die-attach interface changes the local stress and creates a longitudinial stress field. It is also observed that for die-attachmient without voids or some center voids there will be no cracking whereas specimens with voids near the edge of the die inc likely to have verlical (lic cracks. I Tsing the void growth, stress relaxation equations, the void growth is simulated yielding an exponential relationship to void growth and a saturation of void volume with time. Stress relaxation and void growth during cool down are simdlated, once the material puranueters and cooling rates are known. It yields a time dependence of the relative void volume (exponential decay). INTRODUICTTION An important aspect of packaging the semiconductor device is the stability of the die-substrate interface. The chip is nonnally bonded onto a substrate or a package usitg hard solder, soft solder, metal-filled epoxy, or glass. The package together with the (lie bondi-ng layer serves the purposes of heat dissipation, mechanical support, and sometimes electrical conduction. With increasing power requirements of the chip, the quttdity die-allach becomes a special concern. Thermal stress considerations must be taken into account even in a perfectly executed die-attach where the constituent materials have formed a single entity with no voids. Due to thermal expansion nisinatch between the die, the bonding material, and the package, stress is introduced in the cooling step of the bonding process. Stress is generated in the die and may result in cracking. D)ynamnic stress is also produced in the bonded devices when they are subjected to power cycling themal cycling or therlmal shock. Ftilhermore, despite the continuous effort of the electronics industry to produce better die bonds, voids have persistently existed in the bonding layers. These voids have been identified nondestructively using X-ray and scanning acoustic microscopy, or destructive by a sectioning and polishing process or by etching off the entire chip. Voids can occur for various reasons: air entrapment, uneven spreading of the adhesive or solder over the backside of the die, preform outgassing, contamnination of the bonding layer, etc. The presence of voids reduces the reliability of the devices. It is well know that the voids increase the chip operating temperature and that they increase thermnal and mechanical stress failures. In this paper the thermally-induced stresses in the die due to die-attachnment are considered using an analytical method and finite element method (EL;M). Analytical Consideratioti of Thermal St
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