Effect of a Channel Length and Drain Bias on the Threshold Voltage of Field Enhanced Solid Phase Crystallization Polycry
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0989-A17-05
Effect of a Channel Length and Drain Bias on the Threshold Voltage of Field Enhanced Solid Phase Crystallization Polycrystalline Thin Film Transistor on the Glass Substrate Won-Kyu Lee1,2, Sang-Myeon Han1, Sang-Geun Park1, Young-Jin Chang2, Kee-Chan Park3, Chi-Woo Kim2, and Min-Koo Han1 1 School of Electrical Engineering, Seoul National University, Bldg. 130, Rm. 302, Seoul National Univ., San 56-1, Sillim-dong, Gwanak-gu, Seoul, 151-742, Korea, Republic of 2 LCD Business, Samsung Electronics Co., San-24, Nongseo-dong, Giheung-gu, Yongin, 449711, Korea, Republic of 3 Dept. of Electronics Engineering, Konkuk University, Seoul, 143-701, Korea, Republic of ABSTRACT We have fabricated a new magnetic field enhanced solid phase crystallization (FESPC) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which show the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs. The mobility (µ) and threshold voltage (VTH) of p-type TFTs of which the channel width and length are 5 µm and 7 µm, respectively are 31.98 cm2/Vs and -6.14 V, at VDS = -0.1 V. In the FESPC TFTs, the characteristics caused by grain boundary are remarkable due to large number of grain boundaries in the channel compared with poly-Si TFTs. The VTH of the TFT which have 5 µm channel length is smaller than that of 18 µm channel length by 1.36 V, which is considerably large value. It is due to the large number of grain boundaries in the channel and the high lateral electric field. The grain boundary potential barrier height is decreased, when the large lateral electric field is applied (which is called DIGBL effect). As a result of increased mobility, the drain current is increased, and VTH can be decreased. The activation energy (Ea ) is strongly depended on the drain bias and the number of grain boundaries. Ea is decreased, caused by the large drain bias and/or smaller number of grain boundaries. This decreased Ea can be reduced VTH due to increased the drain current. VTH of p-type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary by increased lateral electrical field. INTRODUCTION It is well known that a-Si:H TFTs, which have a considerable attention as pixel elements for active matrix organic light-emitting diodes (AMOLEDs) displays due to an excellent uniformity up to large area [1-4]. However, the electrical performance of a-Si:H TFTs still needs to be improved in respect to mobility and threshold voltage (VTH) shift [5]. Low temperature poly-Si TFTs based on excimer laser crystallization (ELC) method are stable to electrical bias and have high field-effect carrier mobility, but non-uniformity of TFT characteristics which caused by laser shot characteristics should be improved. In order to obtain uniform TFT characteristics and reliable devices without laser energy, several crystallization methods have been proposed [6-7]. Solid phase crystallization (SPC) of a-Si is a
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