Drain Bias Dependent Threshold Voltage Shift of a-Si:H TFT Due to the Pulsed Stress
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0989-A14-03
Drain Bias Dependent Threshold Voltage Shift of a-Si:H TFT Due to the Pulsed Stress Sang-Geun Park, Jae-Hoon Lee, Sang-Myen Han, Sun-Jae Kim, and Min-Koo Han Electrical Engineering and Computer Science, Seoul National University, 130-Dong, 305-Ho, Seoul National University, San 56-1, Shillim-Dong, Gwanak-Gu, Seoul, 151-742, Korea, Republic of ABSTRACT We have investigated the threshold voltage shift (VTH) in the a-Si:H TFTs due to the various negative pulse width stress. The drain bias dependent VTH in the pulsed stress of a-Si:H TFT for AMOLED backplane was also measured and analyzed. When a positive gate and drain bias is applied to a-Si:H TFT (W/L = 200/4 µm), VTH of a-Si:H TFT is increased during the stress time due to the defect state creation and charge trapping. VTH of a-Si:H TFT is increased from 1.645V to 2.53V (∆VTH=0.885V) after the DC gate bias stress of VGS=15V, VDS=0V for 20,000sec. When the pulsed negative bias stress is applied to the gate electrode of the current driving a-Si:H TFT with the drain bias, VTH shift is considerably reduced due to the hole trapping into the gate insulator during the stress. When a negative pulse width is 16msec (pulse of 60Hz), the VTH is increased form 1.594V to 2.195V (∆VTH=0.601V). When a negative pulse width increases from 16msec to 5sec without drain bias (VDS=0V), VTH is increased from 1.615V to 2.055V (∆VTH=0.44V). When a drain bias is increased from 0V to 15V, VTH is slightly decreased from 1.58V to 1.529V (∆VTH=-0.051V) due to large (-30V) VGD (VG=-15V, VD=15V) bias, while it is increased from 1.66V to 2.078V (∆VTH=0.418V) width DC gate bias stress of VGS=15V, VDS=15V for 20,000sec. INTRODUCTION Active matrix organic light emitting diode (AMOLED) employing thin film transistor (TFT) pixels have attracted considerable attentions due to high brightness, compactness and wide viewing angle [1-3]. Recently, poly-Si TFTs are considered as the pixel element of AMOLED due to good electric characteristics such as high mobility and superior stability. However it suffers from a current non-uniformity caused by inherent fluctuation of excimer laser energy. The hydrogenated amorphous silicon (a-Si:H) TFT could be suitable for pixel elements of AMOLED due to an excellent uniformity up to large area with mature fabrication process. However it is well known that the electrical stability of a-Si:H TFT is rather poor. The stability of a-Si:H TFT needs to be improved for high quality AMOLED display circuit. When a positive gate and drain bias is induced in the a-Si:H TFT, VTH of a-Si:H TFT increases over the stress time due to the defect state creation and charge trapping. An increased VTH decreases the brightness of AMOLED display. Recently, we have reported that the negative gate bias annealing can cure a degraded a-Si:H TFT due to the hole trapping into SiNx gate insulator. In this work, the gate electrode of a-Si:H TFT is subjected to the pulsed stress rather than DC negative gate bias stress in order to investigate the negative bias annealing effects on practical
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