Effect of Current Direction on the Reliability of Different Capped Cu Interconnects

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Effect of Current Direction on the Reliability of Different Capped Cu Interconnects C. L. Gan1, C. Y. Lee1, C. K. Cheng2 and J. Gambino3 1 School of Materials Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 2 Institute of Microelectronics, 11 Science Park Road, Singapore 117685 3 IBM Microelectronics, 1000 River Street, Essex Junction, VT 05452, USA ABSTRACT The reliability of Cu M1-V1-M2-V2-M3 interconnects with SiN and CoWP cap layers was investigated. Similar to previously reported results, the reliability of CoWP capped structures is much better than identical SiN capped structures. However, it was also observed that the reliability of CoWP capped interconnects was independent of the direction of electrical current flow. This phenomenon is different from what was observed for SiN capped structures, where M2 lines with electron current flow in the upstream configuration (“via-below”) have about three times larger median-time-to-failure than identical lines in the downstream configuration (“viaabove”). This is because the Cu/SiN interface is the preferential void nucleation site and provides the fastest diffusion pathway in such an architecture. Failure analysis has shown that fatal partially-spanned voids usually had formed directly below the via for “via-above” configuration, and fully-spanned voids occurred in the lines above the vias for “via-below” configuration. On the other hand, failure analysis for CoWP-coated Cu structures showed that partiallyspanned voids below the via do not cause fatal failures in the downstream configuration. This is because the CoWP layer is conducting, and thus able to shunt current around the void. As a result, a large fully-spanning void is required to cause a failure, just like the upstream configuration. Thus the lifetime of an interconnect with a conducting cap layer is independent of whether the current is flowing upstream or downstream. INTRODUCTION Copper-based interconnects have replaced Al-based ones as the choice of on-chip wirings in the current microelectronics industry due to its lower resistivity and better reliability [1-2]. Although the bulk diffusion of Cu is much slower than that of Al, electromigration remains a serious reliability issue for advanced interconnects. It is widely accepted that this lower than expected improvement in electromigration performance is due to faster Cu diffusion along the interfaces. In most Cu interconnects, a Ta-based liner encapsulates the Cu at the sides and bottom, while a dielectric is used to cap on the Cu surface. It has been reported that the electromigration lifetime of Cu damascene interconnects is mostly dependent on the atomic transport along the Cu/dielectric interface [3-6]. A number of studies has been conducted which showed that using a metal-based cap layer (e.g. Ta/TaN, CoWP) will improve the reliability of Cu interconnects over dielectric-capped (e.g. SiNx, SiC, SiCxNyHz) interconnects [7-10]. Previously, it had been shown that the direction of current flow wil

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