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Electromigration Reliability of Dual-Damascene Cu/Oxide Interconnects Ennis T. Ogawa,1 Volker A. Blaschke,2 Alex Bierwag,1 Ki-Don Lee,1 Hideki Matsuhashi,1 David Griffiths,2 Anup Ramamurthi,1 Patrick R. Justison,1 Robert H. Havemann,2 and Paul S. Ho 1 1 Interconnect and Packaging Laboratory, Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712-1100 2 SEMATECH, 2706 Montopolis Dr. Austin, TX 78741-6499 ABSTRACT An electromigration study has determined the lifetime characteristics and failure mode of dual-damascene Cu/oxide interconnects at temperatures ranging between 200 and 325 °C at a current density of 1.0 MA/cm2. A novel test structure design is used which incorporates a repeated chain of “Blech-type” line elements. The large interconnect ensemble permits a statistical approach to addressing interconnect reliability issues using typical failure analysis tools such as focused ion beam imaging. The larger sample size of the test structure thus enables efficient identification of “early failure” or extrinsic modes of interconnect failure associated with process development. The analysis so far indicates that two major damage modes are observable: (1) via-voiding and (2) voiding within the damascene trench. INTRODUCTION The arrival of dual-damascene Cu/oxide interconnects signifies an important change in the type of technologies necessary to achieve successful integration beyond 0.25 µm minimum feature dimension. Yet despite the formidable technological challenges ahead, detailed assessment of dual-damascene interconnect reliability has not been demonstrated publicly. The work here outlines a potentially useful methodology for electromigration (EM) reliability analysis. Two major issues have been targeted: (1) characterization of EM test structures using multiply-linked chains of interconnect elements and (2) determination of EM performance and damage formation mechanism - especially that of “early failures.” [1] EXPERIMENTAL DETAILS Test Structures The samples were prepared at Sematech using 200 mm wafers and consist of two-level interconnect structures based on a Ta/low temperature PVD seed Cu/ electroplated (EP) Cu stack. [2] Above the upper metal level (M2), a SiNx cap/ Al bond pad process is used for outside electrical connections. Heat treatment consists of a short excursion up to roughly 400 °C during nitride passivation, a 30 min. anneal at 325°C in forming gas after wafer processing, and a 35 min. cure at 330 °C for die attach. Consequently, the interconnects show “near bamboo” microstructure. The test structure design (labeled LC) used here is a variation of the design used by I. A. Blech [3] where line elements of different lengths are serially aligned for critical length effect observation. In this version, however, an M2 dual-damascene integration scheme is used, where

D2.3.1

the line dimensions at metal 1 (M1) ensure EM failure above M1 and the serially arranged M2 interconnect elements each receive the same nominal current density. The M2 line elements vary in lengt