Effect of Dielectric Materials on Stress-Induced Damage Modes in Damascene Cu Lines
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Effect of Dielectric Materials on Stress-Induced Damage Modes in Damascene Cu Lines Jong-Min Paik1, Hyun Park1, Ki-Chul Park2, and Young-Chang Joo1 1 School of Materials Science and Engineering, Seoul National University, Seoul 151-744 Korea 2 Advanced Process Development Project Team, System LSI Division, Samsung Electronics Co., Ltd., San 24, Nongseo-Ri, Giheung-Eup, Young-In City, Gyeonggi-Do 449-711 Korea
ABSTRACT Various low-k materials are being pursued as dielectric materials for future interconnects. However, poor thermo-mechanical properties of low-k materials cause tremendous reliability concerns, thus the proper materials for integration with Cu are not suggested yet. In this study, the line width and spacing dependence of damascene Cu lines embedded by TEOS and low-k materials (CORAL) was analyzed using x-ray diffraction. Generally, the hydrostatic stress of Cu/TEOS was greater than that of Cu/CORAL, while the opposite for von-Mises stress. Using a three-dimensional finite analysis (FEA), the effect of low-k materials on the stress and its distribution in via-line structures of dual damascene Cu interconnects was studied. In the case of Cu/TEOS, the hydrostatic stress was concentrated at the via and on the top of the lines, where it was suspected that the void would nucleate. On the other hand, in the via-line structures integrated with organic low-k materials, large von-Mises stress was maintained in the via. Therefore, the deformation of via, rather than voiding, may be the main failure mode in the interconnects with low-k materials. INTRODUCTION Since RC delay and crosstalk are anticipated to be the limiting factors in fabricating the interconnects for the next-generation integrated circuits, copper and low-k dielectrics are being introduced to reduce the electric resistance and the parasitic capacitance [1]. Cu interconnects are fabricated using the damascene process, in which Cu is electrochemically deposited into the trenches and the excessive Cu over the trench is removed using chemical mechanical polishing (CMP). Then the interconnect lines are covered with passivation layers at high temperature (350~400 ) and cooled to room temperature. Large stresses can be built up during successive thermal cycling, due to the differences in the coefficients of thermal expansion (CTE) of the
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component materials [2]. Therefore, failure due to stress in Cu interconnects is one of the major reliability concerns [3, 4]. In this study, the effect of dielectric materials on stress-induced damages of Cu interconnects was investigated. Stresses in Cu damascene lines of various line widths integrated with different IMD (Intermetal Dielectric) materials were measured using x-ray diffraction. After the measurement of stresses in lines, the stress distributions of via-line structures were evaluated using the FEA. Based on these results and calculations, the prediction of failure mechanisms will be given with regard to different dielectric materials. EXPERIMENTAL DETAILS The samples were fabricated using
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