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F7.2.1

Mortality Dependence of Cu Dual Damascene Interconnects on Adjacent Segment C.W. Chang1, C.L. Gan1,2, C.V. Thompson1,3, K.L. Pey1,4, W.K. Choi1,5, N. Hwang6 1

Advanced Materials for Micro- and Nano-Systems, Singapore-MIT Alliance, 4, Engineering Drive 3, Singapore 117576 2 School of Materials Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798 3 Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 4 School of Electrical & Electronics Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798 5 Department of Electrical and Computer Engineering, National University of Singapore, 4, Engineering Drive 3, Singapore 117576 6 Microsystems, Modules & Components Laboratory, Institute of Microelectronics Singapore, 11, Science Park Road, Singapore Science Park II, Singapore 117685

ABSTRACT Three terminal ‘dotted-I’ interconnect structures, with vias at both ends and an additional via in the middle, were tested under a variety of test conditions. Failures (mortalities) were observed even when segments were tested under conditions that would not have led to failure in two-terminal structures. Mortalities were found in right segments with jL values as low as 1250 A/cm, which is lower when compared to the immortality condition (jL)cr of 3700 A/cm reported for similar via-terminated structures. Moreover, we found that the mortality of a dotted-I segment is dependent on the direction and magnitude of the current in the adjacent segment. These results suggest that there is not a definite value of the jL product that defines true immortality in individual segments that are part of an interconnect tree. More importantly, the critical jL value for a single segment of Cu interconnects may be reduced or increased by an adjacent segment. Therefore independently determined (jL)cr values cannot be directly applied to interconnects with branched segments, but rather the magnitude as well as the direction of the current flow in the adjoining segments must be taken into consideration in evaluating the immortality of interconnect segments in an interconnect network.

INTRODUCTION With increasing requirements for high clocking speeds and complex functions for integrated circuits (IC), more metal layers and longer interconnects are incorporated into each single chip. In addition, continued shrinking of interconnect widths leads to higher current densities with each new technology node. The 2003 International Technology Roadmap for Semiconductors [1] predicts that in the year 2005, a total length of 907 m of interconnects in 11 layers will be required in a 1 cm2 chip. At the same time the tolerable interconnect failure rate must be reduced to 5 FITs (5 failures per 109 device-hours) to protect the overall functionality of the chip. This sets a great challenge to the development of a reliable interconnect technology, especially with respect to electromigration resistance.

F7.2.2

Electromigration occurs through a net atomic