The Effect of Gate Geometry on the Charging Characteristics of Metal Nanocrystal Memories
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The Effect of Gate Geometry on the Charging Characteristics of Metal Nanocrystal Memories Authors: Anirudh Gorur-Seetharam, Chungho Lee and Edwin C. Kan Organization: School of Electrical and Computer Engineering, Cornell University Abstract This study presents the effect of gate geometry on the charging characteristics of metal nanocrystal memories. The effect is studied by varying the perimeter to area ratio, number of convex corners and concave corners of the gate of a metal-oxidesemiconductor (MOS) capacitor with embedded gold nanocrystals. It can be observed that the nanocrystal charging rate increases for a smaller perimeter to area ratio. The presence of concave and convex corners increases the nanocrystal charging rate. Based on this study it is expected that gate geometries with low perimeter to area ratio and with selected convex and concave corners would increase the nanocrystal charging rate. Introduction The difference between the two main commercially available memory systems, dynamic RAM (DRAM) and Flash memories, is that DRAM provides fast read/write capability, whereas Flash memories have the advantage of nonvolatile data retention. Metal nanocrystal memories can be designed to have a good combination of both advantageous features. In metal nanocrystal memories the effective potential well designed by metal work function engineering enables the use of an oxide in the direct tunneling regime, where the oxide endurance in repeated write/erase cycles dramatically improves [2]. Also the discrete storage nodes of metal nanocrystal memories provide advantages in the design tradeoffs of write/erase voltage and retention time [1]. The effect of the control gate geometry on the charging characteristics of metal nanocrystal memories was studied by varying the control gate geometry of a metal-oxidesemiconductor (MOS) capacitor with embedded gold nanocrystals. We have considered three types of gate geometries: a circle, a square and a quasi-fractal pattern [3] with the same area. The geometric differences between the three structures are the perimeter to area ratio, the number of convex and concave corners. In this paper, we will present our device design, fabrication process, and structural and electrical characterization. Device design and fabrication An ultra thin (~2 nm) layer of silicon dioxide (tunnel oxide) is first grown thermally on a boron doped (1017 cm-3) p-type silicon substrate. On this tunnel oxide gold nanocrystals are formed by a self-assembly process [2]. A 30nm PECVD oxide (control oxide) is then deposited followed by a 200nm chromium layer deposition by e-beam evaporation. The device structure is schematically shown in Fig 1. This chromium layer is patterned by photolithography into three geometric shapes: circle, square and quasifractal (Fig. 2). The area charge density Q in the oxide consists of charge stored in the
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nanocrystal, fixed oxide charge, mobile oxide charge, and silicon-oxide interface state trapped charge. The amount of charges stored in the nanocrystal scal
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