Metal gate electrode, channel and gate oxide engineering to improve DC and analog/RF performance of double-gate MOSFET f
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Metal gate electrode, channel and gate oxide engineering to improve DC and analog/RF performance of double‑gate MOSFET for high‑speed applications Sanjay1 · B. Prasad1 · Anil Vohra1 Received: 24 February 2020 / Accepted: 20 April 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract In the present work, for high-speed and high-frequency applications, various DC and analog/RF parameters like drain current ( ID ), transconductance (gm ) , output conductance (gd ) , transconductance generation factor (TGF), the cutoff frequency (fT ) , transit time (𝜏) , frequency transconductance product (FTP), channel resistance (Rch ) , direct tunneling current ( IG ) and quasistatic capacitance–voltage (QSCV) characteristics for 10-nm double-gate NMOSFETs of Si and In0.53 Ga0.47 As have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the drift diffusion approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation (to account for quantization). The effect of including conduction band splitting into multiple sub-bands has been taken into account, and the channel region is very lightly doped. The effect of metal gate electrode, channel and gate oxide engineering on ID,gm , TGF, gd , fT , 𝜏 , TFP, Rch , IG and QSCV has been simulated. Also, a comparison of these parameters has been done between Si and In0.53 Ga0.47 As . It was found that except TGF at the higher VGS and IG values for Si, all the other above-mentioned parameters are higher for In0.53 Ga0.47 As . It was found that there is about 7.99 × 105% increase in ION for In0.53 Ga0.47 As as compared to Si. Also, the device has a small drain-induced barrier lowering ~ 8.44 mV/V, almost an ideal subthreshold slope ~ 60 mV/dec and high ION/IOFF ratio ~ 6.30 × 107. Keywords Double-gate NMOSFET · Drain current · DC and analog/RF performance parameters · Direct tunneling current · QSCV
1 Introduction The revolution in the microelectronic industry has sustained due to the scaling of the MOS transistor [1] which has been following Moore’s law for nearly five decades [2]. However, miniaturization faces certain challenges like performance degradation in MOS due to short channel effects (SCEs), viz. drain-induced barrier lowering (DIBL), the threshold voltage (VTH ) roll-off, subthreshold slope (SS) degradation, source–drain charge sharing and subsurface punch through. Further, because of a very thin SiO2 layer, direct tunneling of electrons through the gate insulator takes place [3] and the operating voltage cannot be lowered below 0.8–0.9 V [4].
* Sanjay [email protected] 1
Electronic Science Department, Kurukshetra University, Kurukshetra, Haryana 136119, India
Due to the above limitations and to continue scaling down to the gate length of 50 nm and below, it requires: 1. The use of metal gate electrode engineering which uses non-conventional device structures such as double-gate (DG) MOSFET, which can be scaled down to 10-nm gate length to meet the require
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