Elastic anisotropy of Cu and its impact on stress management for 3D IC: Nanoindentation and TCAD simulation study
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Ude D. Hangen and Thomas Wyrobek Hysitron Inc., Minneapolis, Minnesota 55344
Lay Wai Kong State University of New York, College of Nanoscale Science and Engineering, Albany, New York 12203
Aditya Karmakar and Xiaopeng Xu Synopsys Inc., Mountain View, California 94043
Iuliana Panchenko Technische Universitaet Dresden, Electronics Packaging Laboratory, 01069 Dresden, Germany (Received 4 May 2011; accepted 1 September 2011)
This article presents a study on elastic anisotropy of Cu by indentations at different penetration depth ranges (sub-10 nm, several-10 nm, and several-100 nm), and the impact of elastic anisotropy on the stress in 3D stacked integrated circuits (3D ICs). The reduced modulus, ER, values determined at sub-10 nm indentations on Cu single crystals are very close to the unidirectional values. Similarly, cross-sectional sub-10 nm indentation tests on the Cu grains in a through-silicon via (TSV) show unidirectional ER values. In contrast, the Hill’s average values are observed at several-100 nm indentations. We propose that before lattice rotation happens within a volume beneath the indentation, elastic anisotropy can be strongly reflected in the ER value. When the experimentally measured Cu elastic anisotropy is used in a technology computer-aided design simulation of a Cu-filled TSV, significant impacts are observed on the stress field and the carrier mobility variation in an active Si region.
I. INTRODUCTION
3D stacked integrated circuits (3D ICs) with vertical through-silicon vias (TSVs) are complex structures formed with materials that have very different thermal and mechanical properties. During wafer-level manufacturing, assembly, and packaging operations, the 3D ICs are exposed to a number of thermal cycles. Due to the material property differences like the coefficient of thermal expansion (CTE) between the constituent materials, these thermal cycles lead to thermomechanical stresses in the 3D ICs.1 The process induced thermomechanical stresses could alter the carrier mobility in the MOSFET transistor channel.2 Furthermore, the mechanical stresses affect the reliability of Cu/low-k backend-of-line (BEoL) structures due to the so-called chip–package interaction (CPI) and may lead to cracks and failures.3,4 All of these effects and their correlations with various material and geometry parameters can be examined using physics-based models and advanced numerical simulation tools.5,6 The applications of simulation tools for designing 3D ICs with high transistor and ina)
Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2011.323 J. Mater. Res., Vol. 27, No. 1, Jan 14, 2012
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terconnect density, however, require knowledge of materials behavior at extremely small dimensions and its correlation with the numerical results. Here, nanoindentation and electron backscatter diffraction (EBSD) methods are used to determine the elastic anisotropy and the orientation of Cu grains in a TSV. During the previo
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