Buffer Insertion for 3D IC
Despite the momentum 3D IC technology has gained recently, there has been little progress on timing optimization for 3D ICs. In this chapter, we first study the fact that Through-Silicon-Vias (TSVs) have large parasitic capacitances that increase signal s
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Buffer Insertion for 3D IC
Abstract Despite the momentum 3D IC technology has gained recently, there has been little progress on timing optimization for 3D ICs. In this chapter, we first study the fact that Through-Silicon-Vias (TSVs) have large parasitic capacitances that increase signal slew. Next, we develop a buffer insertion algorithm that improves the delay of both 3D and 2D nets in a 3D IC with explicit consideration of signal slew. The effectiveness of this technique is demonstrated with various nets and full-chip results. Compared with the well-known van Ginneken algorithm and the timingconstraint-based 2D optimization by a commercial software, our algorithm finds buffering solutions with lower slew-aware delay and buffer usage with tolerable runtime overhead.
The materials presented in this chapter are based on [8].
3.1 Introduction For high performance 3D ICs, it is crucial to perform thorough timing optimization, especially when the 3D nets are on timing critical paths. Among timing optimization techniques, buffer insertion is known to be the most effective way. However, currently there is no commercial design software that performs buffer insertion on multiple die designs simultaneously. The through-silicon-vias (TSVs) have a large parasitic capacitance that increases the signal slew and the delay on the downstream. Even for 2D ICs, today’s advanced technology nodes (e.g., 28 nm node) experience high slew degradation along nets, which in turn increases gate delay. L.P.P.P. van Ginneken [15] adopted dynamic programming (VGDP). VGDP has been used in slew buffering [5], which fixes slew design rule violations but does not optimize timing. A non-VGDP buffer insertion algorithm with slew consideration was presented in [13]. However, their delay models could not adopt effective capacS.K. Lim, Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, DOI 10.1007/978-1-4419-9542-1 3, © Springer Science+Business Media New York 2013
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itance [14], and hence considering the fact that TSVs affect effective capacitance much, this algorithm is not suitable for 3D ICs. Also, their framework relies on nonlinear optimization which would incur runtime issues for large net instances, which was not reported. In contrast, the VGDP framework is known for efficiency and flexibility, yet there has been no work that considers realistic signal slew in VGDP framework. In [9] the authors considered slew in VGDP framework, however their slew model is not realistic and the implementation is complicated due to piecewise linear functions. In this chapter we study the bottom-up slew propagation DP (SPDP), which is a modified version of VGDP, to perform delay optimization with the consideration of slew for TSV-based 3D ICs. By considering slew in DP framework, we achieve lower buffered delay compared with the original VGDP. There is a common belief in 3D IC community that timing optimization can be handled with existing 2D electronic design automation (EDA) tools, with a littl
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